NDLI: Design level debugging of timing behavior in embedded systems: Using a model-based approach

Content Provider	IEEE Xplore Digital Library
Author	Iyenghar, P. Westerkamp, C. Wuebbelmann, J. Pulvermueller, E.
Copyright Year	2011
Description	Author affiliation: Software Engineering Research Group, University of Osnabrueck, Germany (Iyenghar, P.; Pulvermueller, E.) \|\| Institute of Computer Engineering, University of Applied Sciences, Osnabrueck, Germany (Westerkamp, C.; Wuebbelmann, J.)
Abstract	A robust model-based debugging and testing technique integrated with the Model Driven Development (MDD) approach for memory size constrained, real-time critical embedded target systems is still in its nascent stages. This is especially true for the industry standard MDD-based tools. In addition, a model-based debugging technique or tool chain based on the newly introduced timing diagrams in UML 2.x is not yet available. In this paper, we discuss a model-based, design-level debugging approach with which the timing behavior of embedded targets is visualized with the aid of UML timing diagrams on the host side, in real-time. The proposed approach is suitable for memory size constrained, real-time embedded target systems as the overhead introduced is negligible, constant and known beforehand. Hence, the end-user has the option to include the overhead in the system design phase, thereby making use of a model-based debug solution and at the same time adhering to temporal constraints. A prototype implementation of the proposed approach is discussed and an illustrative example is presented.
Starting Page	889
Ending Page	894
File Size	660867
Page Count	6
File Format	PDF
ISBN	9781457704352
e-ISBN	9781457704345
e-ISBN	9781457704338
DOI	10.1109/INDIN.2011.6035011
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-26
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real time systems model-based debugging Unified modeling language embedded systems Debugging UML timing diagram Timing Monitoring Embedded software Graphical user interfaces
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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