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Content Provider | IEEE Xplore Digital Library |
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Author | Dongguo Liang Qing Ye |
Copyright Year | 2008 |
Description | Author affiliation: Asic & Syst. Dept., Chinese Acad. of Sci., Beijing (Dongguo Liang; Qing Ye) |
Abstract | A programmable gain amplifier (PGA) was designed for a low-IF GPS receiver. Linearity method which was based on the differential degeneration and gm boost structure was used in the circuit. Transistors which were working in the sub-threshold region were applied in the built-in DC-offset correction circuit. This PGA provided a 96-dB digitally controlled gain range with a step of 6-dB, and the overall gain accuracy was 0.03 dB. The 3dB bandwidth of the PGA was 300 MHz. The noise figure at the maximum gain was 23.7dB. The IIP3 was -5dBm for the minimum gain. The PGA was implemented in a 0.18 um CMOS process and approximately occupied 0.097 mm2. This PGA consumed 3.5 mA at a 1.8 V supply. |
Starting Page | 101 |
Ending Page | 104 |
File Size | 1047110 |
Page Count | 4 |
File Format | |
ISBN | 9781424420636 |
DOI | 10.1109/ICCCAS.2008.4657737 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2008-05-25 |
Publisher Place | China |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Linearity Receivers Global positioning system Bandwidth CMOS integrated circuits Gain Electronics packaging |
Content Type | Text |
Resource Type | Article |
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