NDLI: New scan attacks against state-of-the-art countermeasures and DFT

Content Provider	IEEE Xplore Digital Library
Author	Ali, S.S. Sinanoglu, O. Saeed, S.M. Karri, R.
Copyright Year	2014
Description	Author affiliation: New York Univ. Abu Dhabi (NYUAD), Abu Dhabi, United Arab Emirates (Ali, S.S.; Sinanoglu, O.) \|\| Polytech. Inst. of New York Univ., New York, NY, USA (Saeed, S.M.; Karri, R.)
Abstract	Scan attack has been known as a threat to Design for Testability (DFT). All the existing attacks require both the normal mode and the test mode of the device. In normal mode the intermediate results of a crypto-hardware are captured in scan chains and in the test mode the results are shifted out. One simple countermeasure for this kind of attacks is to reset the device whenever there is a switch of the mode. A recent test-mode-only attack shows that the mode-reset countermeasure is insecure against scan attack. An attack is still possible using only the test mode of the device. However, the attack was presented without the presence of an on-chip test compactor. In this paper we propose a new test-mode-only attack on AES hardware which works in the presence of an on-chip response compactor. The proposed attack retrieves the secret key with negligible time complexity. The attack results show that DFT infrastructures with response compactor are vulnerable to scan attack even in the presence of mode-reset countermeasure.
Starting Page	142
Ending Page	147
File Size	182746
Page Count	6
File Format	PDF
e-ISBN	9781479941124
DOI	10.1109/HST.2014.6855585
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hamming distance Testability Discrete Fourier transforms Switches Scan-based DFT Vectors Compaction System-on-chip Security Scan Chain Scan Attack AES
Content Type	Text
Resource Type	Article

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