NDLI: Hardware Particle Swarm Optimization with passive congregation for embedded applications

Content Provider	IEEE Xplore Digital Library
Author	Munoz, D.M. Llanos, C.H. dos S. Coelho, L. Ayala-Rincon, M.
Copyright Year	2011
Description	Author affiliation: Industrial and Systems Engineering, Graduate Program, LAS/PPGPES, Pontifical Catholic University of Parana, Curitiba, Brazil (dos S. Coelho, L.) \|\| Department of Mechanical Engineering, Automation and Control Group/GRACO, University of Brasilia, Brazil (Munoz, D.M.; Llanos, C.H.) \|\| Department of Computer Science and Mathematics, University of Brasilia, Brazil (Ayala-Rincon, M.)
Abstract	Achieving high performance optimization algorithms for embedded applications can be very challenging, particularly when several requirements such as high accuracy computations, short elapsed time, area cost, low power consumption and portability must be accomplished. This paper proposes a hardware implementation of the Particle Swarm Optimization algorithm with passive congregation (HPPSOpc), which was developed using several floating-point arithmetic libraries. The passive congregation is a biological behavior which allows the swarm to preserve its integrity, balancing between global and local search. The HPPSOpc architecture was implemented on a Virtex5 FPGA device and validated using two multimodal benchmark problems. Synthesis, simulation and execution time results demonstrates that the passive congregation approach is a low cost solution for solving embedded optimization problems with a high performance.
Starting Page	173
Ending Page	178
File Size	290675
Page Count	6
File Format	PDF
ISBN	9781424488476
e-ISBN	9781424488483
DOI	10.1109/SPL.2011.5782644
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-13
Publisher Place	Argentina
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Software algorithms Computer architecture Benchmark testing Hardware Software Field programmable gate arrays Optimization
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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