NDLI: Modeling of switching response of small diameter nanowire field effect transistors

Content Provider	IEEE Xplore Digital Library
Author	Morusupalli, S.P. Verma, A. Basavaraju, S. Buin, A.K. Nekovei, R.
Copyright Year	2010
Description	Author affiliation: Department of Electrical Engineering and Computer Science, Vanderbilt University, Nashville, TN 37212, USA (Morusupalli, S.P.) \|\| Département de Chimie, Université de Montréal, C.P. 6128, Succursale Centre-ville, Montréal, Québec H3C 3J7, Canada (Buin, A.K.) \|\| Department of Electrical Engineering and Computer Science, Texas A&M University-Kingsville, Kingsville, TX 78363, USA (Verma, A.; Basavaraju, S.; Nekovei, R.)
Abstract	We report on a comprehensive modeling of small diameter (< 4 nm) nanowire field effect transistors as switches. The SPICE simulation of the transistor takes data from device and material simulations, and therefore allows for significant flexibility in tool development for nano-devices and circuits. Device simulations involve solving self-consistently the drift-diffusion equation, with Gauss Law in integral form for the electrostatics of the device structure.
Starting Page	278
Ending Page	281
File Size	779379
Page Count	4
File Format	PDF
ISBN	9781424488964
e-ISBN	9781424488971
DOI	10.1109/NMDC.2010.5652474
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	switching response Logic gates Silicon Nanoscale devices Mathematical model Integrated circuit modeling Silicon nanowires FETs
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

Radiation Hard Silicon Nanowire Field Effect Transistors

Integrated nanosystems with junctionless crossed nanowire transistors

Self-aligned multi-channel silicon nanowire field-effect transistors

Nanowire field-programmable computing platform

Atomistic modeling of unintentional single charge effects in silicon nanowire FETs

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs

Si nanowire device and its modeling

Reconfigurable nanowire electronics — Device principles and circuit prospects

Modeling of switching response of small diameter nanowire field effect transistors

Similar Documents

Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs

Radiation Hard Silicon Nanowire Field Effect Transistors

Integrated nanosystems with junctionless crossed nanowire transistors

Self-aligned multi-channel silicon nanowire field-effect transistors

Nanowire field-programmable computing platform

Atomistic modeling of unintentional single charge effects in silicon nanowire FETs

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs

Si nanowire device and its modeling

Reconfigurable nanowire electronics — Device principles and circuit prospects

Modeling of switching response of small diameter nanowire field effect transistors