NDLI: Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture

Content Provider	IEEE Xplore Digital Library
Author	Miro-Panades, I. Clermidy, F. Vivet, P. Greiner, A.
Copyright Year	2008
Description	Author affiliation: Univ. of Pierre et Marie Curie, Paris (Miro-Panades, I.)
Abstract	This paper presents a physical implementation of the DSPIN network-on-chip in the FAUST architecture. FAUST is a stream-oriented multi- application SoC platform for telecommunications addressing IEEE 802.11a and MC-CDMA standards. The original asynchronous network-on-chip (ANOC) of FAUST has been replaced by the multi-synchronous DSPIN network-on-chip. In this paper, we analyze how the DSPIN network-on-chip, originally designed to support shared memory and multi-processors architectures, can support stream-oriented architectures. The physical implementation of both ANOC and DSPIN are presented. Finally, a comparison between ANOC and DSPIN designs in a 130 nm technology is carried out in terms of area, throughput, packet latency, and power consumption.
Starting Page	139
Ending Page	148
File Size	883464
Page Count	10
File Format	PDF
ISBN	0769530982
DOI	10.1109/NOCS.2008.4492733
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-07
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption network-on-chip FAUST NoC DSPIN Memory architecture physical implementation Telecommunication standards Throughput CMOS process Delay Multicarrier code division multiple access Network-on-a-chip bi-synchronous FIFO Frequency Clocks ANOC
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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