NDLI: Quaternary edge-triggered flip-flop with neuron-MOS literal circuit

Content Provider	IEEE Xplore Digital Library
Author	Guoqiang Hang Xuanchang Zhou Yang Yang Xiaohui Hu Xiaohu You
Copyright Year	2013
Description	Author affiliation: Sch. of Inf. Sci. & Eng., Southeast Univ., Nanjing, China (Xiaohu You) \|\| Sch. of Inf. & Electr. Eng., Zhejiang Univ. City Coll., Hangzhou, China (Guoqiang Hang; Xuanchang Zhou; Yang Yang; Xiaohui Hu)
Abstract	A novel CMOS quaternary D-type edge-triggered flip-flop using a single latch with neuron-MOS literal circuits is presented. In the proposed circuit, data are sampled into the latch during a short transparency period for rising edge of the clock signal by using the arrow pulse produced by the race-hazard of the clock signal. The quaternary literal functions are realized by using neuron-MOS transistors without any modification of the thresholds. The benefit of the proposed voltage-mode quaternary flip-flop is that the circuit can be fabricated by standard CMOS process with a 2-ploy layer. Besides, it has a simpler construction with respect to previously reported quaternary flip-flop. The effectiveness of the proposed circuit has been validated by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	1743
Ending Page	1747
File Size	246254
Page Count	5
File Format	PDF
ISBN	9781467347143
ISSN	21579563
DOI	10.1109/ICNC.2013.6818264
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-07-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Latches CMOS circuits neuron-MOS transistor multiple-valued logic Simulation Logic gates Inverters CMOS integrated circuits quaternary flip-flop Transistors floating-gate MOS Flip-flops
Content Type	Text
Resource Type	Article

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