NDLI: Qualification of behavioral level design validation for AMS & RF SoCs

Content Provider	IEEE Xplore Digital Library
Author	Joannon, Yves Beroulle, Vincent Robach, Chantal Tedjini, Smail Carbonero, Jean-Louis
Copyright Year	2007
Description	Author affiliation: ST MICROELECTRONICS, Crolles, France (Carbonero, Jean-Louis) \|\| LCIS-ESISAR (INPG), Valence, France (Joannon, Yves; Beroulle, Vincent; Robach, Chantal; Tedjini, Smail)
Abstract	The expansion of Wireless Systems-on-Chip leads to a rapid development of design and manufacturing methods In this paper, the test vectors used for design validation of AMS & RF SoCs are evaluated and optimized. This qualification is based on a fault injection method. A fault model based on variation of behavioral parameters and a related qualification metric are proposed. This approach is used in the receiver’s design of a WCDMA transceiver. A test set defined by verification engineers during the validation of this system is qualified and optimized. Then, this test set is compared with a second test set automatically generated by a developed tool.
Starting Page	206
Ending Page	211
File Size	163829
Page Count	6
File Format	PDF
ISBN	9781424417094
DOI	10.1109/VLSISOC.2007.4402499
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System testing design validation Design methodology VHDL-AMS Circuit faults Multiaccess communication Circuit testing Test Qualification Radio frequency Automatic testing AMS & RF SoCs Radiofrequency integrated circuits fault injection behavioral modeling Integrated circuit modeling characterization Qualifications
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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