NDLI: A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes

Content Provider	IEEE Xplore Digital Library
Author	Sanghun Lee Chanho Lee
Copyright Year	2006
Description	Author affiliation: Dept. of Electron. Eng., Soongsil, University (Sanghun Lee)
Abstract	The reusability of an IP can be increased when it is developed according to a standard bus interface. Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. We have proposed SNA (SoC network architecture) which is high performance on-chip-bus architecture with SNP (SoC network protocol), to solve the problems of the conventional shared bus. Now, we refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting multiple routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs an extended SNP that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. It guarantees simultaneous multiple channels. Thanks to the small number of interconnection wires, the SNA can also be used for the off-chip bus system
Starting Page	86
Ending Page	91
File Size	361593
Page Count	6
File Format	PDF
ISBN	3901882197
DOI	10.1109/VLSISOC.2006.313209
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-16
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	IFIP
Subject Keyword	Degradation Bridges Protocols System performance Network-on-a-chip Bandwidth Computer architecture Routing Logic Delay
Content Type	Text
Resource Type	Article

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