NDLI: Predictable Worst-Case Execution Time Analysis for Multiprocessor Systems-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Rosén, J. Eles, P. Zebo Peng Andrei, A.
Copyright Year	2011
Abstract	Worst-case execution time analysis is the fundament of real-time system design, and is therefore an area which has been subject to great scientific interest for a long time. However, traditional worst-case execution time analysis techniques assume that the underlying hardware is a monoprocessor system, and this class of hardware platforms is getting less suitable for modern embedded applications, which demand more and more in terms of computational power. For multiprocessor systems, traditional worst-case analysis tools do not produce correct results and can consequently not be used. To solve this problem, we have previously proposed a technique for achieving predictability on multiprocessor systems-on-chip using a shared TDMA bus. One of the main benefits with our approach is that existing, traditional worst-case execution time analysis techniques can, after some small modifications, be applied. In this paper, we describe the nature of these modifications and how to handle different types of multiprocessor architectures.
Starting Page	99
Ending Page	104
File Size	511107
Page Count	6
File Format	PDF
ISBN	9781424493579
DOI	10.1109/DELTA.2011.27
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-17
Publisher Place	New Zealand
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real time systems mpsoc Schedules Time division multiple access Pipelines worst-case execution time analysis Hardware embedded real-time systems Timing predictability Multiprocessing systems
Content Type	Text
Resource Type	Article

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