NDLI: ASIC Implementation of Low Power Decimation Filter for UMTS and GSM Sigma-Delta A/D Converter

Content Provider	IEEE Xplore Digital Library
Author	Chi Zhang Ofner, E.
Copyright Year	2007
Description	Author affiliation: Carinthia Univ. of Appl. Sci., Villach (Chi Zhang; Ofner, E.)
Abstract	This work proposes an ASIC implementation of low power non-recursive decimation filters in a GSM and UMTS dual mode sigma delta ADC. An alternative that saves 70% to 80% power consumption to the standard CIC approach is discussed here with a decimation factor of m-th power of two and m-th power of three. More research is done to find the break-even point between power consumption and silicon area for non-recursive and recursive architectures. The chip is fabricated in 0.35 mum CMOS and consumes 4.72 mW in GSM and 5.54 mW in UMTS mode, both at $V_{dd}=2.5$ V.
Starting Page	224
Ending Page	227
File Size	3005530
Page Count	4
File Format	PDF
ISBN	9781424410736
DOI	10.1109/IWSDA.2007.4408364
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	GSM Energy consumption 3G mobile communication Delta-sigma modulation Application specific integrated circuits Power filters ASIC non-recursive structure Finite impulse response filter Frequency Sampling methods Sigma-Delta A/D converter low power Decimation filter Clocks
Content Type	Text
Resource Type	Article

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ASIC Implementation of Low Power Decimation Filter for UMTS and GSM Sigma-Delta A/D Converter