NDLI: A low-noise 8–12 GHz fractional-N PLL in SiGe BiCMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Follmann, R. Köther, D. Herzel, F. Winkler, F. Heyer, H.-V.
Copyright Year	2010
Description	Author affiliation: IMST GmbH, Carl-Friedrich-Gauß-Str. 2, D-47475 Kamp-Lintfort, Germany (Follmann, R.; Köther, D.) \|\| Humboldt University, Informatik, Unter den Linden 6, D-10117 Berlin, Germany (Winkler, F.) \|\| IHP, Im Technologiepark 25, D-15236 Frankfurt (Oder), Germany (Herzel, F.) \|\| Kayser-Threde GmbH, Wolfratshauser Str. 48, D-81379 Munich, Germany (Heyer, H.-V.)
Abstract	A single-chip low-noise fractional-N PLL with 40 percent tuning range is presented. The design employs two integrated VCOs controlled by three digital and two analog signals. The synthesizer is based on a dual-loop configuration. It is tuneable from 8.1 GHz to 12.4 GHz and features an f/2 output. In integer mode phase noise is below −100 dBc/Hz at all frequency offsets larger than 10 kHz. In fractional mode the phase noise is below −90 dBc/Hz in loop. In integer mode the RMS phase error is as low as 0.53 degree.
Starting Page	98
Ending Page	101
File Size	245973
Page Count	4
File Format	PDF
ISBN	9781424472314
e-ISBN	9782874870170
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-27
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	EUROPEAN MICROWAVE ASSOC
Subject Keyword	Phase noise Synthesizers Voltage-controlled oscillators BiCMOS integrated circuits Phase locked loops Tuning Silicon germanium
Content Type	Text
Resource Type	Article

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