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Content Provider | IEEE Xplore Digital Library |
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Author | Jing Jin Xiaoming Liu Peng Qin Jianjun Zhou |
Copyright Year | 2011 |
Description | Author affiliation: Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics, Shanghai Jiao Tong University, Shanghai 200240, China (Jing Jin; Xiaoming Liu; Peng Qin; Jianjun Zhou) |
Abstract | A ΔΣ fractional-N Phase-Locked Loop (PLL) with fast Auto-Frequency Calibration (AFC) is presented in this paper. The proposed PLL employs a dual-core Voltage Controlled Oscillator (VCO), a programmable Frequency Divider (FD), a Phase/Frequency Detector (PFD), and a replica biased Charge Pump (CP) with static offset current to compensate fractional spur, etc. This PLL is intended for a China Mobile Multimedia Broadcasting (CMMB) TV tuner. The design is implemented in a 0.18-μm CMOS process and occupies an area of 2.1 mm×0.92 mm including the on-chip third-order loop filter and the digital circuits. The simulated power consumption is 10 mA at a 1.8 V supply voltage. The simulation result of the phase noise satisfies the CMMB specification. Also, with the help of a fast AFC scheme, the proposed PLL achieves fast settling performance. The settling time is less than 50 fis in typical case including both coarse tuning and fine tuning. |
Starting Page | 539 |
Ending Page | 542 |
File Size | 217933 |
Page Count | 4 |
File Format | |
ISBN | 9781612848631 |
e-ISBN | 9781612848655 |
DOI | 10.1109/ISICir.2011.6132016 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2011-12-12 |
Publisher Place | Singapore |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Phase noise Voltage-controlled oscillators Radiation detectors Phase frequency detector Phase Noise Phase locked loops Tuning Fractional-N PLL AFC |
Content Type | Text |
Resource Type | Article |
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