NDLI: Bit-serial systolic architecture for 2-D non-separable discrete wavelet transform

Content Provider	IEEE Xplore Digital Library
Author	Mohanty, B.K. Meher, P.K.
Copyright Year	2009
Description	Author affiliation: Dept. of Electronics and Communication Engineering, Jaypee Institute of Engineering and Technology, Raghogarh, Guna, Madhya Pradesh, India-473226 (Mohanty, B.K.) \|\| Department of Communication Systems, Institute for Infocomm Research, 1 Fusionopolis Way, Singapore-138632 (Meher, P.K.)
Abstract	In this paper, we have presented a bit-serial systolic-like architecture for the computation of non-separable two-dimensional discrete wavelet transform (2-D DWT) based on the principle of distributed arithmetic. The computational core of the proposed structure is highly regular and modular. The computations which become redundant due to the decimation process are eliminated to obtain a low-complexity computing algorithm for the 2-D DWT. Moreover, it exploits the advantage of constant wavelet filter-base in the DA-based structure to reduce the hardware-complexity. It is shown that the proposed structure involves very low hardware complexity, and significantly less area-time complexity compared with the existing bit-level designs.
Starting Page	159
Ending Page	162
File Size	296351
Page Count	4
File Format	PDF
ISBN	9789810824686
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-14
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	NANYANG TECHNOLOGICAL UNIV
Subject Keyword	VLSI Very large scale integration Time frequency analysis Discrete wavelet transforms Distributed computing Delay Systolic array Filters Computer architecture Hardware Systolic arrays Distributed arithmetic Discrete Wavelet Transform Arithmetic
Content Type	Text
Resource Type	Article

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