NDLI: A BIST TPG approach for interconnect testing with the IEEE 1149.1 STD

Content Provider	IEEE Xplore Digital Library
Author	Feng, W. Huang, W.K. Meyer, F.J. Lombardi, F.
Copyright Year	1999
Description	Author affiliation: Lucent Technol., Allentown, PA, USA (Feng, W.)
Abstract	In this paper, a novel architecture for built-in self test (BIST) and different designs for both the control and data test pattern generators (CTPG and DTPG) are proposed for interconnect testing using the IEEE standard 1149.1. A general and complete procedure to implement this architecture is also presented. For the DTPG design, the complementary counting sequence (as an example of a maximal independent test set) is used for fault detection. One of the main features of this design is its independence with respect to the type of cell in the chain. A novel design is proposed for the CTPG to avoid damage to the circuit as well as to guarantee 100% fault coverage with low hardware overhead and time complexity.
Starting Page	95
Ending Page	100
File Size	172942
Page Count	6
File Format	PDF
ISBN	0769503152
ISSN	10817735
DOI	10.1109/ATS.1999.810735
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-11-18
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Integrated circuit interconnections Circuit testing Automatic testing Software testing Hardware Sequential analysis Electrical fault detection Circuit faults Boolean functions
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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