NDLI: Interconnect testing of boards with partial boundary scan

Content Provider	IEEE Xplore Digital Library
Author	Robinson, G.D. Deshayes, J.G.
Copyright Year	1990
Description	Author affiliation: GenRad Inc., Concord, MA, USA (Robinson, G.D.; Deshayes, J.G.)
Abstract	It is shown that interconnect testing for boards that mix boundary scan and conventional components can be performed effectively by a four-stage strategy: a conventional shorts test where the tester has access, a scan circuitry integrity test, a fairly conventional boundary scan interconnect test, and a test for shorts between the boundary scan and conventional parts of the circuit, which is new. There are a number of complications so that careful analysis of the results is needed, even for the conventional parts of the test, but this strategy can be used to give a precise, usable diagnosis of the problems. It is noted that a circuit is not necessarily testable just because it contains boundary scan parts. The test access port on those components is a potential weak link, and physical access to those signals is necessary to get good diagnosis. In addition, it may be impossible to diagnose accurately shorts involving nodes with neither physical access nor boundary scan access, and that may even repeatedly not be detectable.
Starting Page	572
Ending Page	581
File Size	843127
Page Count	10
File Format	PDF
ISBN	081869064X
DOI	10.1109/TEST.1990.114070
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-09-10
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Logic testing Integrated circuit interconnections Automatic testing Pins Logic circuits Performance evaluation Terminology Power generation Automatic generation control
Content Type	Text
Resource Type	Article

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