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Content Provider | IEEE Xplore Digital Library |
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Author | Akil, N. van Duuren, M. Golubovic, D.S. Boutchich, M. |
Copyright Year | 2008 |
Description | Author affiliation: NXP-TSMC Res. Center, Leuven (Akil, N.; van Duuren, M.; Golubovic, D.S.; Boutchich, M.) |
Abstract | We have presented a new programming scheme for thick tunnel oxide (4-6nm) SONOS memories. The programming is done with conventional CHEI while erasing is performed with PAHHI. Low voltage $(|V_{CG}|<$ 5V, VDs=5V) is used for program and erase. The programming scheme is favorable for short CG lengths $(L_{CG}<$ 100 nm) and yields good memory characteristics: 5.5V $V_{T}$ window (symmetric around 0V), 100mus program and erase time, endurance of 10k cycles (which demonstrates a good compatibility between CHEI and PAHHI), excellent immunity to gate and drain disturbs, and good memory retention (10 years at 100degC). The presented operation scheme enables the implementation of low cost and reliable embedded SONOS memories with a small EEPROM-like granularity in sub-100 nm CMOS generations without the need for high voltage processing. |
Starting Page | 75 |
Ending Page | 76 |
File Size | 538940 |
Page Count | 2 |
File Format | |
ISBN | 9781424415465 |
DOI | 10.1109/NVSMW.2008.27 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2008-05-18 |
Publisher Place | France |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Low voltage SONOS devices Costs Character generation Electrons Nonvolatile memory CMOS process Tunneling Hot carriers Charge carrier processes |
Content Type | Text |
Resource Type | Article |
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