NDLI: Enhanced fault-tolerant Network-on-Chip architecture using hierarchical agents

Content Provider	IEEE Xplore Digital Library
Author	Valinataj, M. Liljeberg, P. Plosila, J.
Copyright Year	2013
Description	Author affiliation: Dept. of Inf. Technol., Univ. of Turku, Turku, Finland (Liljeberg, P.; Plosila, J.) \|\| Sch. of Electr. & Comput. Eng., Babol Univ. of Technol., Babol, Iran (Valinataj, M.)
Abstract	The reliability is a vital aspect in the design of Network-on-Chip (NoC) based systems because a fault in communication medium may cause an overall system failure. On the other hand, performance degradation is an inescapable consequence of fault-tolerant architectures. In this paper, we propose a fault-tolerant NoC architecture that attains higher performance by using low cost agents in a hierarchical manner. These agents which are distributed all over the network, collect, process, and distribute different fault information. Moreover, we propose an enhanced fault-tolerant and congestion-aware routing method that exploits the classified fault information related to the permanent faults that might occur inside the links, network interfaces and different parts of the routers. The experimental results reveal that the proposed NoC architecture imposes small area and power overheads.
Sponsorship	IEEE Comput. Soc.
Starting Page	141
Ending Page	146
File Size	331118
Page Count	6
File Format	PDF
ISBN	9781467361354
e-ISBN	9781467361361
e-ISBN	9781467361347
DOI	10.1109/DDECS.2013.6549806
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-08
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Circuit faults Fault tolerance Fault tolerant systems Ports (Computers) Nickel Peer-to-peer computing congestion network-on-chip fault-tolerance permanent fault routing algorithm reconfiguration
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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