NDLI: Memory Based Analogue Signal Generation Implementation Issues for BIST

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2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

Foreword to the IEEE DDECS 2007 Workshop

Workshop Committees

Table of contents

New Strategies for System-Level Design

Design and Test of Microfluidic Biochips

Logic Diagnosis and Yield Learning

A Testable Random Bit Generator based on a High Resolution Phase Noise Detection

Test Pattern Compression Based on Pattern Overlapping

Layout to Logic Defect Analysis for Hierarchical Test Generation

Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips

Resource Constrained Co-synthesis of Self-reconfigurable SOPCs

Extended Fault Detection Techniques for Systems-on-Chip

A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing

Memories in Scaled technologies: A Review of Process Induced Failures, Test methodologies, and Fault Tolerance

Architecture for Highly Reliable Embedded Flash Memories

Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology

Accurately Determining Bridging Defects from Layout

FPGA Implementaton of Strongly Parallel Histogram Equalization

Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA's

Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder

A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling

A PMT interface for the Optical Module front-end of a neutrino underwater telescope

A proposal for ASM++ diagrams

Lightweight Multi-threaded Network Processor Core in FPGA

Parts Obsolescence Challenges for the Electronics Industry

Simulation and Characterization of Wireless Data Acquisition RF Systems for Medical Diagnostic Application

Two-Level Logic Synthesis for Low Power Based on New Model of Power Dissipation

A March-Based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories

Avoiding Crosstalk Influence on Interconnect Delay Fault Testing

Instance Generation for SAT-based ATPG

Power Testing of an FPGA based System Using Modelsim Code Coverage capability

XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in both Defective and Defect-free Interconnects

Built in Defect Prognosis for Embedded Memories

March CRF: an Efficient Test for Complex Read Faults in SRAM Memories

Manifestation of Precharge Faults in High Speed DRAM Devices

Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair

An Improved MDCT IP Core Generator with Architectural Model Simulation

A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System

Automatic generation of circuits for approximate string matching

About the Efficiency of Real Time Sequences FFT Computing

Clockless Implementation of LEON2 for Low-Power Applications

Decomposition of Logic Functions in Reed-Muller Spectral Domain

Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor

Establishing a New Course in Reconfigurable Logic System Design

Power Dissipation in Basic Global Clock Distribution Networks

Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters

A Mixed Approach for Unified Logic Diagnosis

Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates

A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services

Multiple Errors Detection Technique for RAM

Test Pattern Generator for Delay Faults

An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques

A Novel Parity Bit Scheme for SBox in AES Circuits

Designing Time-to-Digital Converter for Asynchronous ADCs

Algorithm for DRM Signal Recognition in Time Domain and Hardware Realization

RF Transformer Model Parameters Measurement

Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits

A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs

Flip-Flops and Scan-Path Elements for Nanoelectronics

Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair facility via Variable Accuracy Arithmetic

Dedicated architecture for double precision matrix multiplication in supercomputing environment

Design issues of a low frequency low-pass filter for medical applications using CMOS technology

Feasibility of Image Compression in FPGA based Neural Networks

IP Integration Overhead Analysis in System-on-Chip Video Encoder

Quadrature-Phase Topology of a High Frequency Ring Oscillator

Reticle Exposure Plans for Multi-Project Wafers

Low cost, low power, intelligent brake temperature sensor system for automotive applications

Determining MOSFET Parameters in Moderate Inversion

Evolutionary System for Analog Test Frequencies Selection with Fuzzy Initialization

Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System

Intrusion Detection System Intended for Multigigabit Networks

Open Defects Caused by Scratches and Yield Modelling in Deep Sub-Micron Integrated Circuit

Transition Faults Testing Based on Functional Delay Tests

Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits

Prototyping Generators for on-line test vector generation based on PSL properties

On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata

SAT-Based Equivalence Checking Based on Circuit Partitioning and Special Approaches for Conflict Clause Reuse

Debug Patterns for Efficient High-level SystemC Debugging

Memory Based Analogue Signal Generation Implementation Issues for BIST

Developing Virtual ADC Testing Environment in MAPLE

ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing

MEMS Testing by Vibrating Capacitor

TTTC: Test Technology Technical Council

2006 IEEE Design and Diagnostics of Electronic Circuits and systems

Memory Based Analogue Signal Generation Implementation Issues for BIST

Content Provider	IEEE Xplore Digital Library
Author	Shea, T.O. Grout, I. Ryan, J.
Copyright Year	2007
Description	Author affiliation: Univ. of Limerick, Limerick (Shea, T.O.; Grout, I.; Ryan, J.)
Abstract	An analogue signal generated from a periodically reproduced bitstream pattern from a SigmaDelta modulator output can be used in the testing of mixed-signal devices. This paper discusses an ASIC design which examines the implementation issues and design considerations of single and multi-bit quantizers in memory based analogue signal generation. Special emphasis is placed on multi-bit signal generation in which two methods are explored to overcome the linearity issues associated with multi-bit DACs, without the requirement of additional silicon area.
Starting Page	1
Ending Page	6
File Size	441801
Page Count	6
File Format	PDF
ISBN	1424411610
DOI	10.1109/DDECS.2007.4295321
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-11
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal generators Built-in self-test Voltage Circuit testing Signal design Switches Application specific integrated circuits Pulse modulation Frequency Test pattern generators
Content Type	Text
Resource Type	Article

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