NDLI: Using SOI double-gate MOSFET NDR structures to improve ultra-low power full adder performance

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Table of contents

2007 IEEE Northeast Workshop on Circuits and Systems

2006 IEEE North-East Workshop on Circuits and Systems

The 3rd International IEEE-NEWCAS Conference, 2005.

The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004.

Using SOI double-gate MOSFET NDR structures to improve ultra-low power full adder performance

Content Provider	IEEE Xplore Digital Library
Author	Hassoune, I. Yang, X. O'Connor, I. Navarro, D.
Copyright Year	2008
Description	Author affiliation: Lyon Inst. of Nanotechnol., Lyon Univ., Ecully (Hassoune, I.; Yang, X.; O'Connor, I.; Navarro, D.)
Abstract	In this paper, we propose a new efficient design of a hybrid full adder cell combining two logic styles and a negative differential resistance (NDR) device realized in a fully depleted (FD) silicon on insulator (SOI) double-gate (DG) MOSFET technology. Simulation results show significant (65%) power savings for asymmetric gate workfunction and independent gate control full adders with respect to standard CMOS circuits, with lower device count and comparable delay figures.
Starting Page	347
Ending Page	350
File Size	765243
Page Count	4
File Format	PDF
ISBN	9781424423316
DOI	10.1109/NEWCAS.2008.4606392
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-22
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Adders MOSFET circuits Transistors CMOS integrated circuits Power MOSFET Semiconductor device modeling
Content Type	Text
Resource Type	Article

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