NDLI: Design solutions for preventing process induced ESD damage during manufacturing of interconnects

Content Provider	IEEE Xplore Digital Library
Author	Ackaert, J. Greenwood, B.
Copyright Year	2010
Description	Author affiliation: On semiconductor USA (Greenwood, B.) \|\| On semiconductor, Westerring 15, 9700 Oudenaarde, Belgium (Ackaert, J.)
Abstract	ESD problems are commonly thought to be an electrostatic discharge event through the device pins. All known models like HBM, MM, CDM are based on this assumption. During assembly discharge into devices, directly into the surface is also well known. Pad – related, ESD protective structures are useless against this ESD-surface-discharge-path, called ESDFOS [1]. Little is known however on the impact of simple wafer cleaning/spraying as used frequently during the wafer manufacturing itself. In many cases these processes do include high risks of generating electrostatic charge; subsequent discharge into devices and can easily induce ESD-like events internally in the interconnect circuitry of a device. In this paper, charging induced damage (CID) into common metal interconnect is reported. The damage is caused by the build up of charges on a resist surface during a water rinsing step. This charging is inducing a mirror charge on the interconnect circuitry and results in a discharge through the inter metal dielectric layer (IMD) towards a grounded structure. This CID can lead to direct severe yield loss. In milder cases the damage is difficult to detect but is proven to result in reliability issues. The charging has been detected, measured and evaluated with the help of a non contact surface potential measurement. The phenomena has been characterized and quantified. This paper is describing the occurrence of the failures, the design of the test structures, the measurement results. This work is concluding on how a design can be made safe from ESDFOS during processing by applying the popper layout rules.
Starting Page	98
Ending Page	101
File Size	735918
Page Count	4
File Format	PDF
ISBN	9781424457731
e-ISBN	9781424457755
DOI	10.1109/ICICDT.2010.5510285
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-06-02
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electrostatic discharge Manufacturing processes Integrated circuit interconnections Surface discharges Surface charging Dielectric measurements Pins Semiconductor device modeling Assembly Protection
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design Solutions for Preventing Process Induced ESD Damage during Manufacturing of Interconnects

Solving ESD protection latch-up guard ring issues during electrostatic discharge (ESD) events

ESD robustness and scaling implications of aluminum and copper interconnects in advanced semiconductor technology

IN/INS shorting due to surface ESD

Triz application in device & manufacturing electrostatic discharge control.

Interconnects for device ESD protection

Design of electrostatic discharge event detector

Constant energy device test for electrostatic discharge (ESD) of semiconductor devices

Protection against secondary ESD effects

Design solutions for preventing process induced ESD damage during manufacturing of interconnects

Similar Documents

Design Solutions for Preventing Process Induced ESD Damage during Manufacturing of Interconnects

Solving ESD protection latch-up guard ring issues during electrostatic discharge (ESD) events

ESD robustness and scaling implications of aluminum and copper interconnects in advanced semiconductor technology

IN/INS shorting due to surface ESD

Triz application in device & manufacturing electrostatic discharge control.

Interconnects for device ESD protection

Design of electrostatic discharge event detector

Constant energy device test for electrostatic discharge (ESD) of semiconductor devices

Protection against secondary ESD effects

Design solutions for preventing process induced ESD damage during manufacturing of interconnects