NDLI: AES Embedded Hardware Implementation

Content Provider	IEEE Xplore Digital Library
Author	Mourad, O.-c. Lotfy, S.-M. Noureddine, M. Ahmed, B. Camel, T.
Copyright Year	2007
Description	Author affiliation: Ecole Polytech., Bordj-El-Bahri (Mourad, O.-c.; Lotfy, S.-M.)
Abstract	The paper presents a parallel reconfigurable hardware implementation of the AES cryptographic algorithm developed for an embedded application. This new methodology directly maps a design described in a high level language, Handel-C, to FPGA platforms. The Handel-C approach narrows the gap between performance and flexibility, and thus, reduce the risk of translating a high level prototype into HDLs. It provides a high degree of flexibility from two viewpoints: the language level of abstraction and the hardware reconfiguration. Using Handel-C, we enhanced the performance of the designed unit by applying parallelism and reconfigurability. Our FPGA implementations show that superior performance can be achieved compared with software and hardware implementations counterparts. In particular, our design outperforms most of the other designs in speed. At the same time, the area cost for putting the AES algorithm on the same hardware core is also kept as low as possible.
Starting Page	103
Ending Page	109
File Size	139518
Page Count	7
File Format	PDF
ISBN	9780769528663
DOI	10.1109/AHS.2007.23
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-05
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Field programmable gate arrays Public key cryptography Elliptic curve cryptography High level languages Prototypes Design methodology Embedded system Software prototyping NIST
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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