NDLI: Language-driven Validation of Pipelined Processors using Satisfiability Solvers

Content Provider	IEEE Xplore Digital Library
Author	Mishra, P. Heon-Mo Koo Zhuo Huang
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. & Inf. Sci. & Eng., Florida Univ., Gainesville, FL (Mishra, P.; Heon-Mo Koo; Zhuo Huang)
Abstract	Due to increasing demand for faster computations, deeply pipelined processor architectures are being employed to meet desired system performance. Functional validation of such pipelined processors is one of the most complex and expensive tasks in the current systems-on-chip design methodology. While language-based validation techniques have proposed several promising ideas, many challenges remain in applying them to realistic pipelined processors. This paper describes two practical challenges in this methodology: test generation and equivalence checking. The time and resources required for test generation using the existing approaches can be extremely large for today's pipelined processors. Similarly, traditional equivalence checkers are not useful in the context of language-driven model generation and functional validation. This paper outlines our plan to address these challenges using satisfiability checking
Starting Page	119
Ending Page	126
File Size	140425
Page Count	8
File Format	PDF
ISBN	0769526276
ISSN	15504093
DOI	10.1109/MTV.2005.14
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Automatic testing Microprocessors Information science Computer architecture System performance Design methodology Context modeling Output feedback Tellurium
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Functional Test Generation using Property Decompositions for Validation of Pipelined Processors

Graph-based functional test program generation for pipelined processors

Automatic functional test program generation for pipelined processors using model checking

Functional verification of pipelined processors: a case study

Automatic modeling and validation of pipeline specifications driven by an architecture description language [SoC]

Functional coverage driven test generation for validation of pipelined processors

Design Methodology for Pipelined Heterogeneous Multiprocessor System

Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language (2002)

Design evaluation of pipelined processors using finite state machine analysis with Markov chains

Language-driven Validation of Pipelined Processors using Satisfiability Solvers

Similar Documents

Functional Test Generation using Property Decompositions for Validation of Pipelined Processors

Graph-based functional test program generation for pipelined processors

Automatic functional test program generation for pipelined processors using model checking

Functional verification of pipelined processors: a case study

Automatic modeling and validation of pipeline specifications driven by an architecture description language [SoC]

Functional coverage driven test generation for validation of pipelined processors

Design Methodology for Pipelined Heterogeneous Multiprocessor System

Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language (2002)

Design evaluation of pipelined processors using finite state machine analysis with Markov chains

Language-driven Validation of Pipelined Processors using Satisfiability Solvers