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Content Provider | IEEE Xplore Digital Library |
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Author | Yanxia Gao Shuibao Guo Yanping Xu Shi Xuefang Lin Allard, B. |
Copyright Year | 2009 |
Description | Author affiliation: Lab. AMPERE (CNRS UMR 5005)-INSA-Lyon, Villeurbanne Cedex - France (Shi Xuefang Lin; Allard, B.) || School of Mechanical & Electronic Engineering and Automation, Shanghai University, China (Yanxia Gao; Shuibao Guo; Yanping Xu) |
Abstract | Digital pulse-width modulator (DPWM) is known as the critical module in digital controller application for high-frequency switching mode power supply (SMPS). This paper presents a new Hybrid DPWM architecture operating at high frequency with high resolution. The proposed DPWM takes advantage of the phase-shift function of Digital Clock Manager (DCM) in FPGA, and combines a counter-comparator with a digital dither block. To verify the proposed DPWM, an 11-bit prototype DPWM is implemented on a FPGA-based digitally controlled high-frequency buck converter. Experimental results with constant switching frequency up to 2MHz validate the functionality of the proposed DPWM. This hybrid architecture can operate at high switching frequency while reduce clock frequency so as to save power consumption. |
Starting Page | 1 |
Ending Page | 7 |
File Size | 1670781 |
Page Count | 7 |
File Format | |
ISBN | 9781424438457 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2009-05-20 |
Publisher Place | China |
Access Restriction | Subscribed |
Subject Keyword | Digital control Switched-mode power supply Pulsed power supplies Clocks Switching frequency Space vector pulse width modulation Digital modulation Pulse modulation Field programmable gate arrays Prototypes FPGA implementation DPWM DCM phase-shift digital dither SMPS |
Content Type | Text |
Resource Type | Article |
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