NDLI: Creating options for 3D-SIC testing

Please wait, while we are loading the content...

VLSI Design, Automation and Test(VLSI-DAT)

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test

2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)

M2M: Challenges and opportunities

Innovations in healthcare and semiconductor progress

The quest for a new dimension of system integration

Creating options for 3D-SIC testing

Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process

Sensorless dead-time exploration for digitally controlled switching converters

Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits

A high effieciency DC/DC boost regulator with adaptive off/on-time control

Thermal coupling aware task migration using neighboring core search for many-core systems

A fast and accurate instruction-oriented processor simulation approach

A Cycle Count Accurate TLM bus modeling approach

An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

To 4G mobile communication and beyond

Multimode multiband power amplifier optimization for mobile applications

FDSOI: A differentiator for application processors in consumer and mobile markets

$UltraCMOS^{®}$ technology for high-performance switch paths and tunable components

RF and signal processing technologies for 4G mobile networks

Terahertz electronics: Opportunities, challenges and technologies

A case study: 3-D stacked memory system architecture exploration by ESL virtual platform

Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs

Graph-based optimal reactant minimization for sample preparation on digital microfluidic biochips

Automatic adaptive multi-point moment matching for descriptor system model order reduction

Timing-aware clock gating of pulsed-latch circuits for low power design

A layout-aware automatic sizing approach for retargeting analog integrated circuits

A versatile data cache for trace buffer support

A distributed thread scheduler for dynamic multithreading on throughput processors

A configurable bus-tracer for error reproduction in post-silicon validation

An efficient deadlock-free multicast routing algorithm for mesh-based networks-on-chip

A low-power high-radix switch fabric based on low-swing signaling and partially-activated input lines

Design of thermal management unit with vertical throttling scheme for proactive thermal-aware 3D NoC systems

What happens when circuits grow old: Aging issues in CMOS design

Improving and optimizing reliability in future technologies with high-κ dielectrics

Microscopic degradation models for advanced technology

CMOS reliability: From discrete device degradation to circuit aging

A sub-GHz mostly digital impulse radio UWB transceiver for wireless body sensor networks

Ultrasonic telemetry and neural stimulator with FSK-PWM signaling

Efficient techniques for canceling transceiver noise

A 1V 14kfps smart CMOS imager with tracking and edge-detection modes for biomedical monitoring

A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS

A 4.0/7.5-GHz dual-band LC VCO in 0.18-μm SiGe BiCMOS technology

A 5.2–11.8MHz octa-phase relaxation oscillator for 8-PSK FM-UWB transceiver systems

A 0.3 V low-power temperature-insensitive ring oscillator in 90 nm CMOS process

A low-power dual-mode continuous-time delta-sigma modulator with a folded quantizer

A 3-GS/s 5-bit Flash ADC with wideband input buffer amplifier

Time-domain analog-to-digital converters with domino delay lines

A successive approximation ADC with resistor-capacitor hybrid structure

Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units

A novel processor design flow using processor description language applied to a vector coprocessor

A real-time parallel scalable video encoder for multimedia streaming systems

An information hub for implantable wireless brain machine interface

A view scalable multi-view video decoder system

Real-time salient object detection engine for high definition videos

MIMO fingerprinting-based particle filter for mobile positioning systems

An online recursive ICA based real-time multichannel EEG system on chip design with automatic eye blink artifact rejection

Novel test analysis to improve structural coverage — A commercial experiment

Improve speed path identification with suspect path expressions

An FPGA-based test platform for analyzing data retention time distribution of DRAMs

Aging-aware statistical soft-error-rate analysis for nano-scaled CMOS designs

In and out of the cloud

Silicon-package-board co-design for the eye diagram prediction of a 3Gbps HDMI transmitter

A background calibration technique for fully dynamic flash ADCs

A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V

MVSE: A Multi-core Video decoder System level analytics Engine

Design challenges for analog & mixed signal designs

Case study of yield learning through in-house flow of volume diagnosis

ARM next generation 64bit processors for power efficient compute

Multi-processor debug in SoC and processor designs

Cross-layer dynamic prefetching allocation strategies for high-performance multicores

Worst-case IR-drop monitoring with 1GHz sampling rate

Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology

The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3

A 0.5V/1.0V fast lock-in ADPLL for DVFS battery-powered devices

A low-power delay-recycled all-digital duty-cycle corrector with unbalanced process variations tolerance

A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism

A novel on-chip current-sensing structure for current-mode DC-DC converter

A low-power design methodology for sigma-delta modulators with relaxation of required circuit specifications

A wideband programmable-gain amplifier for 60GHz applications in 65nm CMOS

Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies

Jitter error cancellation technique in digital domain for ADC

Current-mirror miller compensation: An improved frequency compensation technique for two-stage amplifiers

A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash

A process-scalable RF transmitter using 90nm and 65nm Si CMOS

Power and area reduction in multi-stage addition using operand segmentation

Reducing computation redundancy for high-efficiency view synthesis

A practical NoC design for parallel DES computation

Energy-efficient architecture for word-based Montgomery modular multiplication algorithm

A low-error and Rom-free logarithmic arithmetic unit for embedded 3D graphics applications

Hybrid path-diversity-aware adaptive routing with latency prediction model in Network-on-Chip systems

Enabling inter-die co-optimization in 3-D IC with TSVs

On the futility of thermal through-silicon-vias

Electromigration- and obstacle-avoiding routing tree construction

Low-cost testing of TSVs in 3D stacks with pre-bond testable dies

Efficient test and repair architectures for 3D TSV-based random access memories

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test

2009 International Symposium on VLSI Design, Automation and Test

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

2006 International Symposium on VLSI Design, Automation and Test

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).

Creating options for 3D-SIC testing

Content Provider	IEEE Xplore Digital Library
Author	Marinissen, E.J.
Copyright Year	2013
Description	Author affiliation: IMEC, Leuven, Belgium (Marinissen, E.J.)
Abstract	Three-dimensional stacked ICs hold the promise of heterogeneous integration, inter-die connections with increased performance at lower power dissipation, and increased yield and hence decreased product cost. However, all of the above can only become true if 3D-SICs can be properly tested for manufacturing defects. Companies have started to develop their test strategies for these products, and the outcome is largely dependent on (1) the necessity of test generation for specific new 3D defects, (2) the feasibility of access the test targets, and (3) the economic trade-offs involved. Test research is needed to create options for these challenges.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	1
Ending Page	7
File Size	817644
Page Count	7
File Format	PDF
ISBN	9781467344357
e-ISBN	9781467344364
DOI	10.1109/VLDI-DAT.2013.6533800
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-22
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Probes Stacking Testing Integrated circuit interconnections Three-dimensional displays Through-silicon vias Circuit faults
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in