NDLI: Channel analysis of High Speed Digital Module and correlation between simulations and measurements

Content Provider	IEEE Xplore Digital Library
Author	Mazzocchi, S. Giacometti, R. Sassaroli, D.
Copyright Year	2013
Description	Author affiliation: Hardware Dev. Dept., D.&P. Electron. Syst., Frascati, Italy (Mazzocchi, S.; Sassaroli, D.) \|\| Agilent EEsof EDA, Agilent Technol. France, Les Ulis, France (Giacometti, R.)
Abstract	In this paper, Signal integrity (SI) analysis is used to analyze effect of crosstalk on performance of a High Speed Digital Module: its most critical part is simulated by ADS, a simulation tool, and then it is measured by an oscilloscope to verify the correctness of results. Technology trends toward higher speed and device density have increased complexity of PCB design to support fast varying and broadband signals without degrading the SI to unacceptable levels. The SI analysis relies on time-domain simulation of pseudo-random data patterns with at rates about 1 Gb/s. The models, like IBIS and SPICE, are required to describe the electrical behavior of the integrated components involved at interconnect traces. This paper is focused on crosstalk, which is one of the main issues of concern for SI. The final result validation is important to define the limitation of simulation for the pre- and post- layouts of electronic board and to reduce the design risk.
Sponsorship	IEEE Compon., Packag. Manuf. Technol. Soc.
Starting Page	1
Ending Page	4
File Size	1061743
Page Count	4
File Format	PDF
ISBN	9781467356787
e-ISBN	9781467356794
DOI	10.1109/SaPIW.2013.6558320
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-12
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Silicon Crosstalk Connectors Receivers Probes Analytical models Grid Plane Signal Integrity (SI) FPGA Mezzanine Card (FMC) Advanced Design System (ADS) High Speed Circuit Design IBIS SPICE Pseudo Random Bit Sequence (PRBS)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

PCB level SI simulation based on IBIS model for high-speed FPGA system

FPGA Mezzanine Card (FMC) standard

FPGA Mezzanine Card Plus (FMC+)

Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA

FPGA mezzanine card DSP module

HDL Design Architecture for Compatible Multichannel Multi-frequency Rate SERIAL Bit Error Rate Tester (BERT) ASIC IP Core for Testing of High Speed Wireless System Products/Applications

High speed multi-lane LVDS inter-FPGA communication link

Design of multi-interface transport card based on FPGA

Platform • Interfaces Intersil’s High-Speed ADC Evaluation PCB Family to FMC Based Evaluation Platforms • 40MSPS to 500MSPS Operation • SPI Access for ADC Configuration • Compatible with all Intersil High-Speed ADC Daughter Cards Evaluation Platform Overv (2011)

Channel analysis of High Speed Digital Module and correlation between simulations and measurements

Similar Documents

PCB level SI simulation based on IBIS model for high-speed FPGA system

FPGA Mezzanine Card (FMC) standard

FPGA Mezzanine Card Plus (FMC+)

Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA

FPGA mezzanine card DSP module

HDL Design Architecture for Compatible Multichannel Multi-frequency Rate SERIAL Bit Error Rate Tester (BERT) ASIC IP Core for Testing of High Speed Wireless System Products/Applications

High speed multi-lane LVDS inter-FPGA communication link

Design of multi-interface transport card based on FPGA

Platform • Interfaces Intersil’s High-Speed ADC Evaluation PCB Family to FMC Based Evaluation Platforms • 40MSPS to 500MSPS Operation • SPI Access for ADC Configuration • Compatible with all Intersil High-Speed ADC Daughter Cards Evaluation Platform Overv (2011)

Channel analysis of High Speed Digital Module and correlation between simulations and measurements