NDLI: Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning

Content Provider	IEEE Xplore Digital Library
Author	Das, P. Gupta, S.K.
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. Eng.-Syst., Univ. of Southern California, Los Angeles, CA, USA (Das, P.; Gupta, S.K.)
Abstract	All post-silicon tasks - validation, diagnosis, delay testing, and speed-binning - must be carried out by applying vectors to actual chips, and capturing and analyzing responses. Yet, vectors used must be generated and analyzed using pre-silicon models of the circuit. Three comprehensive industrial studies demonstrate that existing approaches for generating such vectors are inadequate, and one major weakness is that existing delay models either do not capture process variations or do not capture advanced delay phenomenon that significantly affect delays. Hence, existing models underestimate the worst case delay leading to selection of non-critical paths and generation of vectors that do not invoke worst case delays. In this paper, we propose a simple notion of bounding approximation and show how it can extend any existing delay model to also capture process variations and to eliminate any underestimation. The main question we investigate is how best to use this approach to select paths and generate or evaluate vectors for post silicon tasks. In particular, we study whether it is better to use this approach to bound simple pin-to-pin delay models or more advanced delay models. At the level of timing analysis, bounded versions of pin-to-pin delay models have lower run-time complexity but looser bounds. However, we conduct path selection for delay testing and vector generation for delay validation and show that bounded versions of more advanced delay models are significantly more efficient in terms of validation cost and runtime complexity.
Sponsorship	IEEE Comput. Soc.
Starting Page	1
Ending Page	6
File Size	380397
Page Count	6
File Format	PDF
ISBN	9781467355421
ISSN	10930167
e-ISBN	9781467355438
DOI	10.1109/VTS.2013.6548901
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delays Integrated circuit modeling Vectors Analytical models Logic gates Approximation methods bounding approximations post-silicon process variations delay models pre-silicon
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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