NDLI: ATPG for scan chain latches and flip-flops

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ATPG for scan chain latches and flip-flops

Content Provider	IEEE Xplore Digital Library
Author	Maka, S.R. McCluskey, E.J.
Copyright Year	1997
Description	Author affiliation: Center for Reliable Comput., Stanford Univ., CA, USA (Maka, S.R.)
Abstract	A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while checking their response. Such tests guarantee the detection of all detectable combinational defects inside the bistable elements. The algorithm is implemented by modifying an existing stuck-at combinational test pattern generator. The number of test patterns generated by the new program is comparable to the number of traditional stuck-at patterns. This shows that this approach is practical for large circuits.
Starting Page	364
Ending Page	369
File Size	563132
Page Count	6
File Format	PDF
ISBN	0818678100
ISSN	10930167
DOI	10.1109/VTEST.1997.600306
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-04-27
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic test pattern generation Flip-flops Circuit testing Circuit faults Logic testing Latches Counting circuits Fault detection Circuit simulation Test pattern generators
Content Type	Text
Resource Type	Article

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