NDLI: High level fault modeling of asynchronous circuits

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Identifying sequentially untestable faults using illegal states

Redundancy removal and test generation for circuits with non-Boolean primitives

High-level test generation using physically-induced faults

A portable ATPG tool for parallel and distributed systems

Testing combinational iterative logic arrays for realistic faults

Verification of transient response of linear analog circuits

A solution for the on-line test of analog ladder filters

Frequency-based BIST for analog circuit testing

A low cost 100 MHz analog test bus

Self-test in a VCM driver chip

On the decline of testing efficiency as fault coverage approaches 100%

The use of IDDQ testing in low stuck-at coverage situations

Cyclic stress tests for full scan circuits

An approach to dynamic power consumption current testing of CMOS ICs

Iddt testing of continuous-time filters

On shrinking wide compressors

Signature analysis and aliasing for sequential circuits

An apparatus for pseudo-deterministic testing

Arithmetic built-in self test for high-level synthesis

Real-time on-board bus testing

Resynthesis for sequential circuits designed with a specified initial state

A distance reduction approach to design for testability

An optimized testable architecture for finite state machines

Testability metrics for synthesis of self-testable designs and effective test plans

RT level testability-driven partitioning

The concept of resistance interval: a new parametric model for realistic resistive bridging fault

High level fault modeling of asynchronous circuits

Checking experiments to test latches

Testability of floating gate defects in sequential circuits

Switch-level modeling of transistor-level stuck-at faults

Simulation of at-speed tests for stuck-at faults

VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits

Fault coverage analysis of RAM test algorithms

Reliability evaluation of combinational logic circuits by symbolic simulation

Improving the efficiency of error identification via signature analysis

Diagnosis of scan path failures

Diagnosis of interconnects and FPICs using a structured walking-1 approach

Detection and location of faults and defects using digital signal processing

Asynchronous multiple scan chains

Partial scan designs without using a separate scan clock

A partial scan methodology for testing self-timed circuits

On the design of at-speed testable VLSI circuits

Scan testing of micropipelines

Test pattern generation for I/sub DDQ/: increasing test quality

Compact test generation for bridging faults under I/sub DDQ/ testing

CURRENT: a test generation system for I/sub DDQ/ testing

Detecting I/sub DDQ/ defective CMOS circuits by depowering

Test preparation for high coverage of physical defects in CMOS digital ICs

Improving topological ATPG with symbolic techniques

A scheduling problem in test generation

Detectable perturbations: a paradigm for technology-specific multi-fault test generation

Compact test sets for industrial circuits

Reducing test application time in scan design schemes

Generation of high quality tests for functional sensitizable paths

Diagnostic of path and gate delay faults in non-scan sequential circuits

On the application of local circuit transformations with special emphasis on path delay fault testability

Circuit design for low overhead delay-fault BIST using constrained quadratic 0-1 programming

Multifault testability of delay-testable circuits

Transformed pseudo-random patterns for BIST

A novel pattern generator for near-perfect fault-coverage

Decompression of test data using variable-length seed LFSRs

Retiming, resynthesis, and partitioning for the pseudo-exhaustive testing of sequential circuits

Synthesis of locally exhaustive test pattern generators

An approach for system tests design and its application

Synthesis of combinational circuits with special fault-handling capabilities

A tool for automatic generation of self-checking data paths

A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers

An experimental evaluation of the differential BICS for I/sub DDQ/ testing

Structural constraints for circular self-test paths

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