NDLI: A self-learning neural-network LSI using neuron MOSFETs

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2015 Symposium on VLSI Technology (VLSI Technology)

2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers

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2012 Symposium on VLSI Technology (VLSIT)

2011 Symposium on VLSI Technology - Digest of Technical Papers

2010 Symposium on VLSI Technology

2009 Symposium on VLSI Technology

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2007 IEEE Symposium on VLSI Technology

2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.

Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005.

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407)

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)

1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325)

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

1997 Symposium on VLSI Technology

1996 Symposium on VLSI Technology. Digest of Technical Papers

1995 Symposium on VLSI Technology. Digest of Technical Papers

Proceedings of 1994 VLSI Technology Symposium

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1992 Symposium on VLSI Technology Digest of Technical Papers

1992 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.92CH3172-4)

Technology trend of flash-EEPROM-Can flash-EEPROM overcome DRAM?

A 0.72 mu m/sup 2/ recessed STC (RSTC) technology for 256 Mbit DRAMs using quarter-micron phase-shift lithography

Micro villus patterning (MVP) technology for 256 Mb DRAM stack cell

A buried-plate trench cell for a 64-Mb DRAM

A native-oxide-free process for 4 nm capacitor dielectrics

Ultra-thin silicon dioxide leakage current and scaling limit

Conductive channel in ONO formed by controlled dielectric breakdown

A new modified HF-last cleaning process for high-performance gate dielectrics

Wafer quality specification for future sub-half-micron ULSI devices

Deep subhalf-micron BiCMOS technology using synchrotron X-ray lithography and its application to 58 ps 2 V CMOS gate array

Trends in single-wafer processing

A high performance BiCMOS technology using 0.25 mu m CMOS and double poly 47 GHz bipolar

An ultra high speed ECL-bipolar CMOS technology with silicon fillet self-aligned contacts

High performance BiCMOS technology design for sub-10 ns 4 Mbit BiCMOS SRAM with 3.3 V operation

A high performance 0.6 mu m BiCMOS SRAM technology with emitter-base self-aligned bipolar transistors and retrograde well for MOS transistors

A high performance polysilicon TFT using RTA and plasma hydrogenation applicable to highly stable SRAMs of 16 Mbit and beyond

An asymmetric memory cell using a C-TFT for ULSI SRAMs

A 3.3 V operation nonvolatile memory cell technology

BiFAMOS technology for high speed mega-bit EPROMs

A novel cell structure for giga-bit EPROMs and flash memories using polysilicon thin film transistors

High-rate-gas-flow microwave plasma etching of silicon

Highly anisotropic microwave plasma etching for high packing density silicon patterns

Sensor fusion for ULSI manufacturing process control

Rapid thermal multiprocessing using multivariable control of circularly symmetric 3 zone lamp

FRACS (fully radiative current path structure)-A high speed bipolar transistor with sub-0.1 mu m emitter

Perimeter effects in small geometry bipolar transistors

Single-poly bipolar transistor with selective epitaxial silicon and chemo-mechanical polishing

A novel selective SiGe epitaxial growth technology for self-aligned HBTs

A new salicide process (PASET) for sub-half micron CMOS

0.1 mu m contact metallization with SiH/sub 2/F/sub 2/-reduced CVD W

A novel selective Ni/sub 3/Si contact plug technique for deep-submicron ULSIs

A high performance Si on Si multichip module technology

A highly reliable sub-half-micron via and interconnect technology using Al alloy high-temperature sputter filling

Influence of stress-induced void formation on electromigration endurance in quarter-micron aluminum interconnects

Parameterized SPICE subcircuits for submicron multilevel interconnect modeling

A self-learning neural-network LSI using neuron MOSFETs

High performance 0.1- mu m room temperature Si MOSFETs

A high performance asymmetric LDD MOSFET using selective oxide deposition technique

High drivability and high reliability MOSFETs with non-doped poly-Si spacer LDD structure (SLDD)

Design considerations for sub-0.35 mu m buried channel P-MOSFET devices

Enhanced hot-carrier degradation due to water in TEOS/O/sub 3/-oxide and water blocking effect of ECR-SiO/sub 2/

Suppression of the MOS transistor hot carrier degradation caused by water desorbed from intermetal dielectric

AC hot-carrier effect under mechanical stress (MOSFET)

Wafer-mapping of hot carrier lifetime due to physical stress effects (MOSFET)

An epitaxial emitter cap, SiGe-base bipolar technology with 22 ps ECL gate delay at liquid nitrogen temperature

A new CMOS structure for low temperature operation with forward substrate bias

A high performance low temperature 0.3 mu m CMOS on SIMOX

Photolithographic system using modified illumination

Quarter micron KrF excimer laser lithography

Application of blind method to phase-shifting lithography

Repair technique for phase shifting masks using silicon-containing resist

Lithography for 0.25 mu m and below using simple high-performance optics

A Si bipolar transistor with f/sub max/ of 40 GHz and its application to a 35 GHz 1/16 dynamic frequency divider

A 35-GHz 20- mu m/sup 2/ self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs

1991 Symposium on VLSI Technology

Digest of Technical Papers.1990 Symposium on VLSI Technology

1987 Symposium on VLSI Technology. Digest of Technical Papers

1986 Symposium on VLSI Technology. Digest of Technical Papers

1985 Symposium on VLSI Technology. Digest of Technical Papers

1984 Symposium on VLSI Technology. Digest of Technical Papers

1983 Symposium on VLSI Technology. Digest of Technical Papers

1982 Symposium on VLSI Technology. Digest of Technical Papers

1981 Symposium on VLSI Technology. Digest of Technical Papers

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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