NDLI: Performance considerations in embedded DSP based system-on-a-chip designs

Content Provider	IEEE Xplore Digital Library
Author	Gupte, A. Mehendale, M. Ramamritham, R. Nair, D.
Copyright Year	2001
Description	Author affiliation: DSP Design, Texas Instrum., India (Gupte, A.)
Abstract	Embedded DSP applications require large amount of high performance memory. Today's DSP systems typically have more than a megabit of on-chip memory, as compared to less than a hundred kilo-bits a few years ago. Memory performance can easily become a bottleneck in the system performance. This problem is compounded by the increasing interconnect delay factor at sub-micron technology. A high performance DSP core cannot alone guarantee a high performance system. In this paper, we address the challenges encountered in a high performance embedded DSP based design. We describe performance enhancing techniques ranging from careful physical placement, and logic design to optimal repeater insertion and buffering schemes. A methodology that efficiently addresses the interconnect effects is presented.
Sponsorship	Broadcom India
Starting Page	36
Ending Page	41
File Size	554486
Page Count	6
File Format	PDF
ISBN	0769508316
ISSN	10639667
DOI	10.1109/ICVD.2001.902637
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-01-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing System-on-a-chip Random access memory System performance Decoding Digital signal processing chips Delay effects Access protocols Hip Instruments
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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