NDLI: Hierarchical test generation for systems on a chip

Content Provider	IEEE Xplore Digital Library
Author	Tupuri, R.S. Abraham, J.A. Saab, D.G.
Copyright Year	2000
Description	Author affiliation: Texas Microprocessor Div., Adv. Micro Devices Inc., Austin, TX, USA (Tupuri, R.S.)
Abstract	The rapid increase in functionality on a single chip in the last few years has increased the gap between the complexity of the design and the capability of commercial test tools. In particular the test needs for systems on a chip (SOC) are not addressed by existing tools. Because some of the cores integrated on a single SOC may not have embedded testability features, it is not always possible to use conventional design for testability (DFT) methodologies directly. This paper presents a novel approach for generating tests for complex SOCs which targets one module (or core) at a time, by extracting its environment elegantly in the form of constraints and storing it as virtual logic. Information about the core processor and internal bus is used to reduce the size of the virtual logic so that a commercial ATPG tool can be used to generate tests. These tests are then automatically translated to system-level tests. The approach is illustrated with an example SOC based on the picoJava core.
Starting Page	198
Ending Page	203
File Size	62410
Page Count	6
File Format	PDF
ISBN	0769504876
ISSN	10639667
DOI	10.1109/ICVD.2000.812609
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-01-03
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System testing System-on-a-chip Automatic testing Hip Design for testability Integrated circuit testing Microprocessors Jacobian matrices Automatic test pattern generation Moore's Law
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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