NDLI: A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology

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2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

Semiconductor industry: the name of the game

A top-down look at bottom-up electronics

Clock generation and distribution for the third generation Itanium/spl reg/ processor

A post-silicon clock timing adjustment using genetic algorithms

Clock generation and distribution for intel Banias mobile microprocessor

A design for digital, dynamic clock deskew

21.5 dBm power-handling 5 GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with Depletion-layer-Extended Transistors (DETs)

3-dimensional vertical parallel plate capacitors in an SOI CMOS technology for integrated RF circuits

Very wide tuning range micro-electromechanical capacitors in the MUMPs process for RF applications

Selective metal parallel shunting inductor and its VCO application

A low-power microcontroller having a 0.5 /spl mu/A standby current on-chip regulator with dual-reference scheme

An integrated digital controller for DC-DC switching converter with dual-band switching

High-throughput asynchronous datapath with software-controlled voltage scaling

Accurate modeling of transistor stacks to effectively reduce total standby leakage in nano-scale CMOS circuits

A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface using novel eye-tracking method

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization

A 0.9 V 9 mW 1MSPS digitally calibrated ADC with 75 dB SFDR

A 1.8 V, 1 MS/s, 85 dB SNR 2+2 mash /spl Sigma//spl Delta/ modulator with /spl plusmn/0.9 V reference voltage

A fourth order continuous-time complex sigma-delta ADC for low-IF GSM and EDGE receivers

A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering

A cost-efficient dynamic Ternary CAM in 130 nm CMOS technology with planar complementary capacitors and TSR architecture

Destructive-read random access memory system buffered with destructive-read memory cache for SoC applications

The Umbrella Cell: a logic-process-compatible 2T cell for SOC applications

A memory using one-transistor gain cell on SOI(FBC) with performance suitable for embedded DRAM's

A 10-mW 3.6-Gbps I/O transmitter

A 27-mW 3.6-Gb/s I/O transceiver

A CMOS 3.5 Gbps continuous-time adaptive cable equalizer with joint adaptation method of low-frequency gain and high-frequency boosting

3 Gbps, 5000 ppm spread spectrum SerDes PHY with frequency tracking phase interpolator for serial ATA

RF CMOS comes of age

T-engine: the open, real-time embedded-systems platform for ubiquitous computing

A 1-V CMOS/SOI bluetooth RF transceiver for compact mobile applications

Gain calibration and feedforward automatic gain control for CMOS radio-frequency ICs

A CMOS IF transceiver with 90 dB linear control VGA for IMT-2000 application

A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-/spl mu/m CMOS

A 0.5-14-GHz 10.6-dB CMOS cascode distributed amplifier

An optimally transformer coupled, 5 GHz quadrature VCO in a 0.18 /spl mu/m digital CMOS process

13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider

A 5-GHz CMOS double-quadrature receiver for IEEE 802.11a applications

640/spl times/480 Real-time range finder using high-speed readout scheme and column-parallel position detector

Hotplate-based conductometric monolithic CMOS gas sensor system

A non-uniformity correction scheme using multiple analog buses for an uncooled infrared sensor

A new single chip optical CMOS detector for next generation optical storage systems

Bitline/plateline reference-level-precharge scheme for high-density chainFeRAM

A novel access scheme suppressing disturbance for a cross-point type ferroelectric memory

An adaptive reference generation scheme for 1T1C FeRAMs

A 64 Mbit embedded FeRAM utilizing a 130 nm, 5LM Cu/FSG logic process

Low jitter Butterworth delay-locked loops

10 GHz, 20 mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a 0.18 /spl mu/m digital CMOS process

A design of a compact 2 GHz-PLL with a new adaptive active loop filter circuit

A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis

On-die droop detector for analog sensing of power supply noise

Study of substrate noise and techniques for minimization

Enhanced thermal management for future processors

A process variation compensating technique for sub-90 nm dynamic circuits

Embedded twin MONOS flash memories with 4 ns and 15 ns fast access times

A 512 kB MONOS type flash memory module embedded in a microcontroller

An application specific embeddable flash memory system for non-volatile storage of code, data and bit-streams for embedded FPGA configurations

A high-speed 128 Kbit MRAM core for future universal memory applications

A bootstrapping technique to improve the linearity of CMOS passive mixers

Low 1/f noise and DC offset RF mixer for direct conversion receiver using parasitic vertical NPN bipolar transistor in deep n-well CMOS technology

A 1 Volt switched transconductor mixer in 0.18 /spl mu/m CMOS

A 410-mW, 1.22-GHz downconverter in a dual-conversion tuner IC for OpenCable/spl trade/ applications

A 90 nm 1 GHz 22 mW 16/spl times/16-bit 2's complement multiplier for wireless baseband

A 90 nm 6.5 GHz 256/spl times/64 b dual supply register file with split decoder scheme

3-Transistor antifuse OTP ROM array using standard CMOS process

A wide range 1.0 V-3.6 V 200 Mbps, push-pull output buffer using parasitic bipolar transistors

A 90 nm low power 32 K-byte embedded SRAM with gate leakage suppression circuit for mobile applications

A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias

A fully synchronized, pipelined, and re-configurable 50 Mb SRAM on 90 nm CMOS technology for logic applications

Cosmic-ray multi-error immunity for SRAM, based on analysis of the parasitic bipolar effect

A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology

A CMOS 33-mW 100-MHz 80-dB SFDR sample-and-hold amplifier

A floating-gate-MOS-based low-power CDMA matched filter employing capacitance disconnection technique

Efficient on-chip global interconnects

Closed-form analytical thermal model for accurate temperature estimation of multilevel ULSI interconnects

The Flexible Processor-dynamically reconfigurable logic array for personal-use emulation system

A low cost high performance register-controlled digital DLL for 1 Gbps/spl times/32 DDR SDRAM

A low jitter, fast recoverable, fully analog DLL using tracking ADC for high speed and low stand-by power DDR I/O interface

Built-in duty cycle corrector using coded phase blending scheme for DDR/DDR2 synchronous DRAM Application

Charge-transferred presensing and efficiently precharged negative word-line schemes for low-voltage DRAMs

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

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1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)

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