NDLI: An integrated 12 bit analog front end for CCD based image processing applications

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2015 Symposium on VLSI Circuits (VLSI Circuits)

2014 Symposium on VLSI Circuits Digest of Technical Papers

2013 Symposium on VLSI Circuits

2012 Symposium on VLSI Circuits (VLSIC)

2011 Symposium on VLSI Circuits - Digest of Technical Papers

2010 Symposium on VLSI Circuits

2009 Symposium on VLSI Circuits

2008 IEEE Symposium on VLSI Circuits

2007 IEEE Symposium on VLSI Circuits

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005.

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525)

2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)

1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)

Symposium 1997 on VLSI Circuits

1996 Symposium on VLSI Circuits. Digest of Technical Papers

1996 Symposium on VLSI Circuits. Digest of Technical Papers

Limitations and challenges of multi-gigabit DRAM circuits

Analog circuit design in scaled CMOS technology

A low power data holding circuit with an intermittent power supply scheme for sub-1V MT-CMOS LSIs

A low-power current-sensing complementary pass-transistor logic (LCSCPTL) for low-voltage high-speed applications

Self resetting logic register and incrementer

FCL (FET coupled logic) circuit for 1.5 V, multi-GHz BiCMOS LSIs

Power-on contention elimination [CMOS digital circuits]

A 2-GHz 1.6-mW phase-locked loop

An analytical model of planar inductors on lowly doped silicon substrates for high frequency analog design up to 3 GHz

A 1.8-GHz low-phase-noise spiral-LC CMOS VCO

A 1.5 V, 1.5 GHz CMOS low noise amplifier

The IDCT processor on the adder-based distributed arithmetic

A selfconfigurable digital neuro chip addressing to multi-network architecture

A scalable multiprocessor architecture for professional digital audio

A modular architecture for a 6.4-Gbyte/s, 8-Mbit media chip

A microcontroller embedded with 4 Kbit ferroelectric non-volatile memory

2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell

The charge-share modified precharge-level (CSM) architecture for high-speed and low-power ferroelectric memory

A small data-line-swing read/write scheme for high-endurance nonvolatile DRAMs with ferroelectric capacitors

A fully integrated low noise RF frequency synthesizer design for mobile communication application

A direct digital synthesizer with interpolation circuits

A 30-mW 10.7-MHz pseudo-N-path sigma-delta band-pass modulator

A CMOS channel-select filter for a direct-conversion wireless receiver

A power-optimized CMOS baseband channel filter and ADC for cordless applications

Demonstration of 5T SRAM and 6T dual-port RAM cell arrays

A board level parallel test and short circuit failure repair circuit for high-density, low-power DRAMs

A cost-oriented two-port unified cache for low-power RISC microprocessors

A compact on-chip ECC for low cost flash memories

Negative heap pump for low voltage operation flash memory

Future of the multimedia home PC

The development of lithium ion secondary batteries

A high-resolution, compact, and low-power ADC suitable for multi-channel implementation: measurements and methods of self-calibration

A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter

An integrated 12 bit analog front end for CCD based image processing applications

A 3 V CMOS video acquisition channel

A 2/sup nd/-order double-sampled /spl Delta//spl Sigma/ modulator with individual-level averaging

Low voltage high speed circuit designs for giga-bit DRAMs

Technique for controlling effective Vth in multi-Gbit DRAM sense amplifier

A 0.9 V sense-amplifier driver for high-speed Gb-scale DRAMs

An efficient charge recycle and transfer pump circuit for low operating voltage DRAMs

Capacitance coupled bus with negative delay circuit for high speed and low power (10 GB/s<500 mW) synchronous DRAMs

A 4 Gsamples/s line-receiver in 0.8 /spl mu/m CMOS

A 960 Mbps/pin interface for skew-tolerant bus using low jitter PLL

A data recovery circuit for burst signal using 440 MHz CMOS direct phase controlled VCO

A 156 Mbps CMOS clock recovery circuit for burst-mode transmission

A 0.8 V/100 MHz/sub-5 mW-operated mega-bit SRAM cell architecture with charge-recycle offset-source driving (OSD) scheme

A 2 ns access, 500 MHz 288 Kb SRAM macro

A 500 MHz 1 Mb on-chip cache design using multi-level bit line sensing scheme

A deep sub-V, single power-supply SRAM cell with multi-V/sub T/, boosted storage node and dynamic load

A 285 MHz 6-port plesiochronous router chip with non-blocking cross-bar switch

A 15 mW 1.6 Gb/s wormhole data router for 2-D meshes

Receiver with constant active termination

A 700 Mbps/pin CMOS signalling interface using current integrating receivers

A 50% noise reduction interface using low-weight coding

A programmable low-voltage micropower CMOS input stage architecture

A high bandwidth constant g/sub m/ and slew-rate rail-to-rail CMOS amplifier circuit for embedded low-voltage applications

Novel design techniques for high-linearity MOSFET-only switched-capacitor circuits

An automatic tuning scheme for G/sub m/-C filters with an integrator as master

An efficient controller for variable supply-voltage low power processing

New TSPC latches and flipflops minimizing delay and power

A low-power video motion estimation array processor

An energy-efficient single-chip FFT processor

A 120 mm/sup 2/ 64 Mb NAND flash memory achieving 180 ns/byte effective program speed

A high speed programming scheme for multi-level NAND flash memory

A 2.7 V only 8 Mb/spl times/16 NOR flash memory

20-Mb/s erase/record flash memory by asymmetrical operation

Hybrid phase locked loop system for PRML disk drive read channels

A mixed-signal RAM decision-feedback equalizer for disk drives

A 3 V video signal processing LSI using only bipolar technology

Simulation and analysis of substrate coupling in realistically-large mixed-A/D circuits

All Verilog mixed-signal simulator with analog behavioral and noise models

A dual layer bitline DRAM array with Vcc/Vss hybrid precharge for multi-gigabit DRAMs

Skew minimization techniques for 256M-bit synchronous DRAM and beyond

Flexible test mode design for DRAM characterization

Noise suppression scheme for giga-scale DRAM with hundreds of I/Os

A long data retention SOI-DRAM with the body refresh function

Digest of Technical Papers., Symposium on VLSI Circuits.

Proceedings of 1994 IEEE Symposium on VLSI Circuits

Symposium 1993 on VLSI Circuits

1992 Symposium on VLSI Circuits Digest of Technical Papers

1991 Symposium on VLSI Circuits

Digest of Technical Papers., 1990 Symposium on VLSI Circuits

Symposium 1989 on VLSI Circuits

Symposium 1988 on VLSI Circuits

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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