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Content Provider | IEEE Xplore Digital Library |
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Author | Ogawa, E.T. Lee, K.-D. Matsuhashi, H. Ko, K.-S. Justison, P.R. Ramamurthi, A.N. Bierwag, A.J. Ho, P.S. Blaschke, V.A. Havemann, R.H. |
Copyright Year | 2001 |
Description | Author affiliation: Lab. for Interconnect & Packaging, Texas Univ., Austin, TX, USA (Ogawa, E.T.) |
Abstract | Electromigration (EM) study at temperatures from 325-400/spl deg/C and current densities from 1-2 MA/cm/sup 2/ has determined the failure time characteristics and failure behavior of submicron dual-damascene Cu/oxide interconnects. The test structures used are based on statistical concepts potentially suitable to address the early failure issue in sub-/spl mu/m interconnects and are designed to examine failures occurring only in dual-damascene interconnects. A combination of single and repeated (N=1, 10, 50, and 100) serial chains of nominally identical interconnects are used in conjunction with statistical analysis based on weakest-link concepts (Nelson, 1990) to identify differences in the failure distribution as larger collections of interconnect elements are sampled. In total, nearly 10,000 interconnects were tested using this configuration. Through the use of these multiply-linked interconnect ensembles, statistical evidence of two distinct (weak and strong) failure modes in dual-damascene Cu/oxide interconnects is first reported. The bimodal failures have also been identified with distinct void formation mechanisms that appear characteristic of the dual-damascene interconnect architecture. The weak mode is found to be void formation within the dual-damascene via, while the strong mode is associated with voiding in the dual-damascene trench. The weak mode activation energy is found to be about 1 eV and seems consistent with void formation controlled by interface diffusion between Cu metal and Ta diffusion barrier. These observations using this type of testing methodology confirm the utility of the multi-link approach in electromigration reliability analysis and the detection of early failures. |
Sponsorship | IEEE Electron Devices Soc. |
Starting Page | 341 |
Ending Page | 349 |
File Size | 1244497 |
Page Count | 9 |
File Format | |
ISBN | 0780365879 |
DOI | 10.1109/RELPHY.2001.922925 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2001-04-30 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Statistics Electromigration Testing Grain boundaries Surface resistance Atherosclerosis Metallization Joining processes Laboratories Packaging |
Content Type | Text |
Resource Type | Article |
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