NDLI: Fault model for VLSI circuits reliability assessment

Content Provider	IEEE Xplore Digital Library
Author	Lisenker, B. Mitnick, Y.
Copyright Year	1999
Description	Author affiliation: Intel Israel (74) Ltd., Haifa, Israel (Lisenker, B.)
Abstract	A new fault model, based on the general percolation theory applied to long-channel CMOS VLSI circuits, has been recently introduced. It was shown that a reliability risk appears only when process-related defects create a pattern independent current path in standby mode. An acceptable reliability risk defines a pass/fail criteria. A screening technique, based on this model, presents a strong correlation between rejected devices and early failure rate. In this paper, the general percolation approach was applied to short-channel CMOS VLSI circuits. Unlike long-channel CMOS VLSI, defect-free short-channel CMOS VLSI circuits inherently have a pattern independent standby current, which results from a short-channel MOSFET current in the off state. In this case, the defect related component of this current may be released only by means of a multi-parameter failure criterion. Experimental results that confirm this conclusion are presented and discussed. The reliability risk assessment technique employing this model shows a strong correlation between rejected devices and long term reliability for 32-bit 0.35 /spl mu/m CMOS microprocessors.
Starting Page	319
Ending Page	326
File Size	660633
Page Count	8
File Format	PDF
ISBN	0780352203
DOI	10.1109/RELPHY.1999.761633
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-03-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Very large scale integration Semiconductor device modeling CMOS technology MOSFET circuits Ultra large scale integration Testing Monitoring Integrated circuit reliability Integrated circuit interconnections
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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