NDLI: Parallel switch level fault simulation algorithm/complexity verification using compiled code VHDL

Content Provider	IEEE Xplore Digital Library
Author	Ryan, C.A. Tront, J.G.
Copyright Year	1993
Description	Author affiliation: Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA (Ryan, C.A.; Tront, J.G.)
Abstract	Switch level faults, as opposed to traditional gate level faults, can more accurately model the physical faults found in integrated circuits. Existing fault simulation techniques have a worst-case computational complexity of O(n2), where n is the number of devices in the circuit. A parallel hardware accelerated fault simulator (PHAFS) has been proposed in order to reduce the complexity to O(L2), where L is the number of levels of switches encountered when traversing from output to input. The paper presents the algorithm/complexity verification as needed for the prototyping of PHAFS. The verification includes a compiled code VHDL switch level fault simulator.
Starting Page	100
Ending Page	105
File Size	414996
Page Count	6
File Format	PDF
ISBN	0818643005
DOI	10.1109/IWRSP.1993.263191
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-06-28
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Circuit faults Computational modeling Circuit simulation Integrated circuit modeling Switching circuits Computational complexity Hardware Acceleration Prototypes
Content Type	Text
Resource Type	Article

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Parallel switch level fault simulation algorithm/complexity verification using compiled code VHDL