NDLI: A 5.8-GHz two-stage high-linearity low-voltage low noise amplifier in a 0.35-/spl mu/m CMOS technology [WLANs]

Content Provider	IEEE Xplore Digital Library
Author	Ren-Chieh Liu Chung-Rung Lee Huei Wang Chorng-Kuang Wang
Copyright Year	2002
Description	Author affiliation: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan (Ren-Chieh Liu; Chung-Rung Lee; Huei Wang; Chorng-Kuang Wang)
Abstract	A 5.8-GHz two-stage high-linearity low-voltage CMOS low-nose amplifier (LNA) has been developed in a 0.35-/spl mu/m pure digital CMOS technology without any additional mask or post-processing steps. A two-stage architecture is used to simultaneously optimize the gain and noise performance. Based on the modified CMOS model valid for RF range, the LNA with fully on-chip input, output and inter-stage matching was designed to verify the two-stage LNA architecture. This LNA chip achieves measured results of 3.2-dB NF, +6.7-dBm IIP3 and -3.7-dBm output P/sub 1dB/ at 5.8 GHz. A figure-of-merit for linearity (output IP3/P/sub DC/) of 1.2 is achieved, which is believed to be among the best reported for a CMOS low-noise amplifier operating at 5-6 GHz ISM band. The effective circuit area is only 0.63 /spl times/ 0.46 mm/sup 2/.
Sponsorship	IEEE Microwave Theory and Techniques Soc. IEEE Electron Devices Soc. IEEE Solid States Circuits Soc
Starting Page	221
Ending Page	224
File Size	386021
Page Count	4
File Format	PDF
ISBN	0780372468
ISSN	15292517
DOI	10.1109/RFIC.2002.1012036
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low-noise amplifiers Radiofrequency amplifiers CMOS technology Performance gain Semiconductor device modeling Radio frequency Impedance matching Semiconductor device measurement Noise measurement Linearity
Content Type	Text
Resource Type	Article

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