NDLI: Design of a single event upset (SEU) mitigation technique for programmable devices

Content Provider	IEEE Xplore Digital Library
Author	Baloch, S. Arslan, T. Stoica, A.
Copyright Year	2006
Description	Author affiliation: Inst. for Syst. Level Integration, Alba Centre, Livingston (Baloch, S.; Arslan, T.)
Abstract	This paper presents a unique SEU (single event upset) mitigation technique based upon temporal data sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses both conventional static SEUs and SETs (single event transients) induced errors that can result in data loss for reconfigurable architectures. The proposed scheme not only eliminates all SEUs and SETs and but also all double event upsets as well. This approach permits FPGAs and other microcircuits with deep submicron feature size to be used in space environments. The result are included to show that the proposed scheme is over 40% area efficient than previously introduced schemes
Starting Page	4
Ending Page	345
File Size	172206
Page Count	342
File Format	PDF
ISBN	0769525237
DOI	10.1109/ISQED.2006.46
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-03-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Single event upset Field programmable gate arrays Circuits Microelectronics Random access memory NASA Reconfigurable architectures Ionizing radiation Programmable logic arrays Latches
Content Type	Text
Resource Type	Article

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Design of a single event upset (SEU) mitigation technique for programmable devices