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Content Provider | IEEE Xplore Digital Library |
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Author | Seongkyun Shin Yungseon Eo Eisenstadt, W.R. Jongin Shim |
Copyright Year | 2004 |
Description | Author affiliation: Dept. of Electr. & Comput. Eng., Hanyang Univ., Kyungki-Do, South Korea (Seongkyun Shin; Yungseon Eo) |
Abstract | In today's UDSM(ultra-deep-sub-micron)-process-technology-based ICs, dynamic delay variations of strongly coupled lines (due to neighboring net switching activity) make static timing analysis problematic. In this paper, new analytical timing models for RLC coupled lines are presented and their accuracy is verified. Coupled interconnect lines are decoupled into an effective single line model by using effective capacitances and effective inductances corresponding to switching activity. Their signal transient waveforms of the effective single line models are determined by exploiting the TWA (Traveling-wave-based Waveform Approximation) technique. This is followed by single line analytical timing model development. It is shown that the models have excellent agreement with SPICE simulations for various circuit performance parameters such as line pitch, line length, driver/receiver size, IMD-thickness, and aspect ratio. |
Sponsorship | IEEE Electron Devices Soc. IEEE Componants, Packaging and Manufacturing Technol. Soc. |
Starting Page | 337 |
Ending Page | 342 |
File Size | 397239 |
Page Count | 6 |
File Format | |
ISBN | 0769520936 |
DOI | 10.1109/ISQED.2004.1283697 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2004-03-22 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Coupled mode analysis Delay effects Timing Integrated circuit interconnections Analytical models Capacitance SPICE Circuit simulation Circuit optimization Driver circuits |
Content Type | Text |
Resource Type | Article |
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