NDLI: Formulae for performance optimization and their applications to interconnect-driven floorplanning

Content Provider	IEEE Xplore Digital Library
Author	Chang, N.C.-Y. Yao-Wen Chang Jian, I.H.-R.
Copyright Year	2002
Description	Author affiliation: Global Unichip Corp., Hsinchu, Taiwan (Chang, N.C.-Y.)
Abstract	As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are the most effective and popular techniques to reduce interconnect delay and are traditionally applied to post-layout, optimization. As the SIA technology roadmap predicts, however, the number of interconnections among different blocks and that of buffers inserted in a chip for performance optimization will grow dramatically. It is obviously infeasible to insert/size hundreds of thousands buffers or wires during the post-layout stage when most routing regions are occupied. Therefore, it is critical to incorporate buffer-block and., wire-size planning into floorplanning to ensure timing closure and design convergence. In this paper, we first derive continuous buffer insertion/sizing and wire sizing formulae for performance optimization under a more accurate wire model, and then apply the formulate to interconnect-driven floorplanning that considers not only the buffer-block planning but also wire-size planning.
Sponsorship	IEEE Tech. Committee on VLSI Design (TCVLSI) IEEE Comput. Soc. Tech. Committee on Design Autom. (TCDA) IEEE Comput. Soc. Test Technol. Tech. Council (TTTC) IEEE Electron. Devices Soc. Fabless Semicond. Associates (FSA) ACM/sigDA
Starting Page	523
Ending Page	528
File Size	1764883
Page Count	6
File Format	PDF
ISBN	0769515614
DOI	10.1109/ISQED.2002.996798
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-03-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wire Integrated circuit interconnections Capacitance Circuit optimization Delay effects Timing Iris Hip Convergence Circuit topology
Content Type	Text
Resource Type	Article

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