NDLI: Verifying interoperability and application performance of PDCs in synchrophasor system solution

Content Provider	IEEE Xplore Digital Library
Author	Yufan Guan Kezunovic, M. Sprintson, A. Muxi Yan
Copyright Year	2012
Description	Author affiliation: Department of Electrical and Computer Engineering, Texas A&M University, College Station, USA (Yufan Guan; Kezunovic, M.; Sprintson, A.; Muxi Yan)
Abstract	This paper presents a new test methodology for verifying the interoperability and application performance of synchrophasor system solution containing PMUs, PDCs, and communication network. Two types of tests are defined to evaluate the performance of synchrophasors system components from two different aspects: design and application tests. The interoperability between PMUs and PDCs can be verified by a design test. A fault location algorithm using two-end synchronized measurement is used to evaluate the application performance. We have developed a special device, referred to as “Imparator.” that can emulate different network conditions by introducing impairments such as packet losses and delays. In addition, the imperator can measure performance characteristics of PDCs, such as data processing time. Nine commercial PMUs, three PDCs, and reference GPS receiver are selected to perform the tests. The test results at the end show that the PDCs meet the most of the functional requirements, and interoperability issues exist between the PMUs and PDCs of different vendors.
Starting Page	1
Ending Page	6
File Size	949883
Page Count	6
File Format	PDF
ISBN	9781467323062
e-ISBN	9781467323086
e-ISBN	9781467323079
DOI	10.1109/NAPS.2012.6336388
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phasor measurement units Delay Communication networks Fault location fault location phasor measurement unit (PMU) phasor data concentrator (PDC) intelligent electronic device (IED) synchrophasor power grid
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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