NDLI: Co salicide technology for sub-0.15 /spl mu/m FD-SOI and beyond: super-flat silicide and fully-silicided source/drain structure

Content Provider	IEEE Xplore Digital Library
Author	Ichimori, T. Hirashita, N.
Copyright Year	1999
Description	Author affiliation: VLSI Res. Center, Oki Electr. Ind. Co. Ltd., Tokyo, Japan (Ichimori, T.)
Abstract	Fully-depleted SOI devices have excellent characteristics for low power applications, in such regards as low subthreshold swing, low source/drain (S/D) capacitance and small floating body effect compared to bulk devices or partially-depleted SOI devices (Imai et al, 1998; Chen et al, 1999). These features derive from the thin SOI layer whose typical thickness is less than 50 nm; however, silicidation of such thin SOI films makes device fabrication extremely difficult. In order to keep sheet resistance low enough even in narrow lines many methods have been proposed to date, but they are not applicable to FD-SOI devices because FD-SOI devices require much higher silicide uniformity. Another important issue to overcome is reduction of the parasitic source/drain series resistance. This work presents a solution for such ultra-thin SOI layers in the fabrication of ULSI devices. The new salicide is applied to the fabrication of sub-0.20 /spl mu/m FD CMOS devices on ultra-thin SOI substrates to investigate the validity of the FD-CMOS structure where S/D Si is completely consumed (fully silicided).
Starting Page	72
Ending Page	73
File Size	169111
Page Count	2
File Format	PDF
ISBN	0780363892
ISSN	1078621X
DOI	10.1109/SOI.2000.892775
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-10-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicides Immune system Silicidation Fabrication Substrates Semiconductor films Annealing Rough surfaces Surface roughness Surface morphology
Content Type	Text
Resource Type	Article

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