NDLI: Neural recording system with low-noise analog front-end and comparator-based cyclic ADC

Content Provider	IEEE Xplore Digital Library
Author	Kim, S. Seung-In Na Tae-Hoon Kim Hyunjoong Lee Sunkwon Kim Cyuyeol Rhee Suhwan Kim
Copyright Year	2012
Description	Author affiliation: Department of Electrical Engineering and Computer Science, Seoul National University 1 Gwanak-Ro, Gwanak-Gu, Seoul 151-742, Korea (Kim, S.; Seung-In Na; Tae-Hoon Kim; Hyunjoong Lee; Sunkwon Kim; Cyuyeol Rhee; Suhwan Kim)
Abstract	This paper describes a low-noise neural recording integrated circuit composed of a low-noise analog front-end (AFE) and a low-power analog-to-digital converter (ADC). The AFE amplifies biopotentials and the ADC converts input signal to digital output. The AFE exhibits 53.4dB of mid-band gain, 38.8Hz–10.6kHz of −3dB bandwidth. Total input referred noise (IRN) of AFE is 10.8μVrms and noise efficiency factor (NEF) is 8.1. The ADC achieves 10bit resolution and operates at 2.5MS/s. The chip is fabricated and successfully tested in a 0.18μm CMOS process.
Starting Page	110
Ending Page	114
File Size	1735666
Page Count	5
File Format	PDF
ISBN	9781467312943
ISSN	21641706
e-ISBN	9781467312950
DOI	10.1109/SOCC.2012.6398393
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Noise Bandwidth Electronics packaging Power demand Integrated circuits Charge transfer Analog-digital conversion
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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