NDLI: ASIC implementation of a high speed WGNG for communication channel emulation [white Gaussian noise generator]

Content Provider	IEEE Xplore Digital Library
Author	Fung, E. Leung, K. Parimi, N. Purnaprajna, M. Gaudet, V.C.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada (Fung, E.; Leung, K.; Parimi, N.; Purnaprajna, M.; Gaudet, V.C.)
Abstract	A design for a white Gaussian noise generator (WGNG) is modified and implemented as a 0.18-/spl mu/m CMOS digital ASIC for high-speed communication channel emulation. The original design was implemented using an FPGA. The goal of the work presented is to enhance the performance of the WGNG in order to achieve emulation of high-speed communication standards unattainable by the FPGA implementation. This is accomplished by pipelining the original design and implementing it using an ASIC. A layout is generated, based on a standard digital design flow provided by the Canadian Microelectronics Corporation (CMC). This implementation achieves an output rate of 182 Msamples/sec, which exceeds the speed of the original FPGA implementation by more than seven times.
Sponsorship	The Inst. of Electr. and Electron. Eng. The IEEE Signal Processing Soc. The IEEE Circuits and Syst. Soc
Starting Page	304
Ending Page	309
File Size	342202
Page Count	6
File Format	PDF
ISBN	0780385047
DOI	10.1109/SIPS.2004.1363067
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits Communication channels Emulation Field programmable gate arrays Communication systems Communication standards Gaussian noise Testing AWGN Hardware
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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