NDLI: Fast VLSI binary addition

Content Provider	IEEE Xplore Digital Library
Author	Parhi, K.K.
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA (Parhi, K.K.)
Abstract	This paper presents novel architectures for fast binary addition which can be implemented using multiplexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and recasting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wt/sub fa/ to Wt/sub mux/ where t/sub fa/ and t/sub mux/, respectively, represent binary full adder and multiplexer delays, and W is the word-length. A family of fast converter architectures is developed based on tree-type (obtained using look-ahead techniques) and carry-select approaches. The carry-generation component is the critical component in redundant-to-binary conversion and binary addition. It is shown that, if the word-length, W, is a power of two, then all carry signals can be generated in log/sub 2/Wt/sub max/ time using W(log/sub 2/W-1)+1 multiplexers using a tree-type converter. It is shown that fastest binary addition can be performed using (Wlog/sub 2/W+1) multiplexers in time (log/sub 2/W+1)t/sub max/. If the specified converter latency is greater than log/sub 2/W/sub mux/, then a family of converters using fewest multiplexers can be designed based on carry-select approach. It is shown that the power consumption in carry-select adders is minimized by increasing the number of segments in the adder.
Starting Page	232
Ending Page	241
File Size	499222
Page Count	10
File Format	PDF
ISBN	0780338065
ISSN	15206130
DOI	10.1109/SIPS.1997.626129
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-11-05
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Multiplexing Added delay Energy consumption Computer architecture Encoding Power generation Signal generators Digital arithmetic Algorithm design and analysis
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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