NDLI: Logical Effort model for CNFET-based circuits

Content Provider	IEEE Xplore Digital Library
Author	Ali, M. Ahmed, M. Chrzanowska-Jeske, M.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Portland State Univ., Portland, OR, USA (Ali, M.; Ahmed, M.; Chrzanowska-Jeske, M.)
Abstract	Carbon Nano-Tube Field Effect Transistors (CNFETs) are considered to be a promising candidate beyond the conventional CMOSFET. It is due to their higher current drive capability, ballistic transport, lesser power delay product and better thermal stability. CNFETs specific parameters, such as number of tubes, pitch (spacing between the tubes) and the diameter of CNTs determine current driving capability, speed, power consumption and area of circuits. Logical Effort (LE) technique is used for quick and accurate estimation of delay in large CMOS circuits. Due to specific to CNFET parameters LE technique developed for CMOS cannot be directly transferred to CNFET circuits. We present a newly developed Logical Effort model for CNFET-based circuits that includes influence of CNFET specific parameters. Our model results in fairly accurate delay estimation with an average error around 5% for a set of tested CNFET circuits. The inclusion of CNFET technology parameters in the model ensures the scalability of the model with technology nodes.
Starting Page	460
Ending Page	465
File Size	504844
Page Count	6
File Format	PDF
ISBN	9781479956227
DOI	10.1109/NANO.2014.6968105
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-18
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electron tubes CNTFETs Logic gates Integrated circuit modeling Delays Computational modeling Inverters Logical Effort Carbon Nanotube (CNT) Carbon Nanotube Field Effect Transistor (CNFET) Delay
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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