NDLI: Reliability and device scaling challenges of trapping charge flash memories

Content Provider	IEEE Xplore Digital Library
Author	Yeh, C.C. Tsai, W.J. Lu, T.C. Liao, Y.Y. Zous, N.K. Chen, H.Y. Tahui Wang Wenchi Ting Ku, J. Chih-Yuan Lu
Copyright Year	2004
Description	Author affiliation: Technol. Dev. Center, Macronix Int. Co. Ltd., Hsin-Chu, Taiwan (Yeh, C.C.; Tsai, W.J.; Lu, T.C.; Liao, Y.Y.; Zous, N.K.)
Abstract	As flash memories move toward the giga-bits era, several challenges limit their scalability. Floating gate flash memories face the problems of un-scalable tunnel oxide, and the last technology node of NOR flash was predicted to be 65 nm, based on the extrapolation of the difference between physical and electrical cell dimensions vs. generations, which drops to zero at 45 nm. Although SONOS-type flash memories show better scalability and simpler process, there are still some difficulties. In this paper, three SONOS-type flash memories (SONOS, NROM and PHINES) are compared and the scaling problems and reliability issues are disclosed.
Starting Page	247
Ending Page	250
File Size	222129
Page Count	4
File Format	PDF
ISBN	0780384547
DOI	10.1109/IPFA.2004.1345612
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-07-08
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flash memory Channel hot electron injection Electron traps SONOS devices Scalability Electronics industry Industrial electronics Reliability engineering Nonvolatile memory Extrapolation
Content Type	Text
Resource Type	Article

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