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Content Provider | IEEE Xplore Digital Library |
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Author | Rao, R.A. Mathew, L. Sarkar, D. Smith, S. Saha, S. Garcia, R. Stout, R. Gurmu, A. Ainom, M. Onyegam, E. Xu, D. Jawarani, D. Fossum, J. Banerjee, S. Das, U. Upadhyaya, A. Rohatgi, A. Wang, Q. |
Copyright Year | 2012 |
Description | Author affiliation: National Renewable Energy Laboratories, Golden, CO 80401, USA (Wang, Q.) || Georgia Institute of Technology, Atlanta, 30332, USA (Upadhyaya, A.; Rohatgi, A.) || AstroWatt, Austin TX 78758 USA (Rao, R.A.; Mathew, L.; Smith, S.; Saha, S.; Garcia, R.; Stout, R.; Gurmu, A.; Ainom, M.; Xu, D.; Jawarani, D.) || University of Texas, Austin, 78758 USA (Onyegam, E.; Banerjee, S.) || Institute for Energy Conversion, University of Delaware, Newark, 19716, USA (Das, U.) || University of Florida, Gainesville, 32611, USA (Sarkar, D.; Fossum, J.) |
Abstract | The crystalline Si photovoltaic industry has been scaling down the Si wafer thickness in order to reduce costs and potentially attain higher efficiencies by minimizing bulk recombination. However, cell manufacturers are struggling to reduce the wafer thickness below 150µm as there are no economically viable technologies for manufacturing very thin Si wafers and such thin silicon wafers impose stringent handling requirements as wafer breakage and yield loss impact final module cost. We have previously reported a novel kerfless exfoliation technology capable of producing ultra thin 25µm thin flexible mono c-Si foils from thick Si wafers. In this work, we report on scaling the technology to 8-inch diameter wafers. A 25µm thin exfoliated monocrystalline Si solar cell with a front heterojunction emitter and a diffused back surface field structure has been fabricated with a power conversion efficiency of 14.9%. Simulations show that with optimized texturing of the foil and better surface passivation, higher efficiencies (20%) can be attained. We have also fabricated dual heterojunction devices on 25µm thin exfoliated Si, which show high V of 680mV. Due to the kerfless exfoliation process and wafer reuse, a final cell cost of $0.30/Wp can be achieved. |
Starting Page | 001837 |
Ending Page | 001840 |
File Size | 737252 |
Page Count | 4 |
File Format | |
ISBN | 9781467300643 |
ISSN | 01608371 |
e-ISBN | 9781467300667 |
DOI | 10.1109/PVSC.2012.6317951 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2012-06-03 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Silicon Heterojunctions Metals Surface treatment Implants MONOS devices Photovoltaic cells silicon kerfless thin crystalline heterojunction photovoltaic cells |
Content Type | Text |
Resource Type | Article |
Subject | Industrial and Manufacturing Engineering Control and Systems Engineering Electrical and Electronic Engineering |
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