NDLI: Implementing a scalable ASC processor

Content Provider	IEEE Xplore Digital Library
Author	Hong Wang Walker, R.A.
Copyright Year	2003
Description	Author affiliation: Comput. Sci. Dept., Kent State Univ., OH, USA (Hong Wang; Walker, R.A.)
Abstract	Previous papers (Walker et al. (2001); Wu et al. (2002)) have described our implementation of a small prototype processor and control unit for associative computing, called the ASC processor. That initial prototype was implemented on an Altera education board using an Altera FLEX 10K FPGA, and was limited to an unrealistic 4 processing elements (PE). This paper describes a more complete implementation - a scalable ASC processor that can scale up to 52 PE on an Altera APEX 20KE board, or further on larger FPGA. This paper also proposes extensions to support multiple control units and control parallelism.
Sponsorship	IEEE Comput. Soc Tech. Committee on Parallel Process. IEEE Comput. Soc. Tech. Committee on Comput. Archit. IEEE Comput. Soc. Tech. Committee on Distrib. Process. ACM SIGARCH
File Size	348672
File Format	PDF
ISBN	0769519261
ISSN	15302075
DOI	10.1109/IPDPS.2003.1213482
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-04-22
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Prototypes Circuits Registers Field programmable gate arrays Parallel processing Associative processing Computer aided instruction Switches Logic arrays Arithmetic
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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